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1. 发明授权

US5965930A High frequency bipolar transistor and method of forming the same 失效
标题翻译：高频双极晶体管及其形成方法
公开(公告)号：US5965930A
公开(公告)日：1999-10-12
申请号：US964001
申请日：1997-11-04
申请人： Kurt K. Sakamoto , Peter J. Zdebel , Michael G. Lincoln
发明人： Kurt K. Sakamoto , Peter J. Zdebel , Michael G. Lincoln
IPC分类号： H01L29/73 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/732
CPC分类号： H01L29/0821 , H01L29/0649 , H01L29/7322 , H01L2224/05554 , H01L2224/48237 , H01L2924/1305 , H01L2924/30107 , H01L2924/3011
摘要： A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.
摘要翻译：在衬底（61）上形成具有减小的电容和电感的高频双极晶体管（30,60）。衬底（61）被重掺杂以形成低电阻电流通路。轻掺杂的外延层（62）将衬底（61）与形成晶体管的层分离。外延层（62）与基板（61）的导电类型相同。顶侧衬底接触（73）将晶体管（60）的发射极耦合到衬底（61）。基板（61）的背面被金属化并且导电地附接到引线框架（51）的引线标记，从而消除晶体管的发射极中的引线键合电感。

2. 发明授权

US5886374A Optically sensitive device and method 失效
标题翻译：光敏装置及方法
公开(公告)号：US5886374A
公开(公告)日：1999-03-23
申请号：US2801
申请日：1998-01-05
申请人： Kurt K. Sakamoto , Peter J. Zdebel , Christopher K. Y. Chun
发明人： Kurt K. Sakamoto , Peter J. Zdebel , Christopher K. Y. Chun
IPC分类号： H01L27/144 , H01L31/062 , H01L31/075 , H01L31/105 , H01L31/113
CPC分类号： H01L27/1443
摘要： A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).
摘要翻译：一种工艺结合了高性能硅pin二极管（60）和诸如晶体管，电阻器和电容器的其它半导体器件。 pin二极管（60）形成在器件的外延层（44）的下方，其深度使得波长大于约600纳米的光的吸收最大化。诸如晶体管的器件形成在外延层（44）中。集成电路具有衬底（41），本征掺杂层（42），掩埋层（43）和外延层（44）。隔离区域（45）隔离本征掺杂区域（46），掩埋层区域（47）和外延层区域（48）。 pin二极管（32）具有衬底（41），本征掺杂区域（46）和掩埋层区域（47）。多晶硅区域（62）提供针二极管（60）的顶侧接触。

3. 发明申请

US20110193160A1 ELECTRONIC DEVICE INCLUDING A BURIED INSULATING LAYER AND A VERTICAL CONDUCTIVE STRUCTURE EXTENDING THERETHROUGH AND A PROCESS OF FORMING THE SAME 有权
标题翻译：包括绝缘绝缘层的电子器件和通过其延伸的垂直导电结构及其形成方法
公开(公告)号：US20110193160A1
公开(公告)日：2011-08-11
申请号：US12702055
申请日：2010-02-08
申请人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
发明人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/66696 , H01L21/26586 , H01L21/2815 , H01L21/743 , H01L21/823475 , H01L27/1203 , H01L29/0626 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1008 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/42376 , H01L29/6625 , H01L29/66659 , H01L29/66689 , H01L29/735 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.
摘要翻译：电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域相对于主表面更靠近对置的表面。电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

4. 发明授权

US07276747B2 Semiconductor device having screening electrode and method 有权
标题翻译：具有屏蔽电极和方法的半导体器件
公开(公告)号：US07276747B2
公开(公告)日：2007-10-02
申请号：US11112570
申请日：2005-04-25
申请人： Gary H. Loechelt , Peter J. Zdebel
发明人： Gary H. Loechelt , Peter J. Zdebel
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L21/2815 , H01L29/0878 , H01L29/407 , H01L29/41766 , H01L29/42376 , H01L29/66719 , H01L29/66727
摘要： In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region.
摘要翻译：在一个实施例中，半导体器件形成在半导体材料体中。半导体器件包括与沟道区间隔开的屏蔽电极。

5. 发明授权

US06809396B2 Integrated circuit with a high speed narrow base width vertical PNP transistor 有权
标题翻译：具有高速窄基极宽垂直PNP晶体管的集成电路
公开(公告)号：US06809396B2
公开(公告)日：2004-10-26
申请号：US10303168
申请日：2002-11-25
申请人： Peter J. Zdebel , Misbahul Azam , Gary H. Loechelt , James R. Morgan , Julio C. Costa
发明人： Peter J. Zdebel , Misbahul Azam , Gary H. Loechelt , James R. Morgan , Julio C. Costa
IPC分类号： H01L2973
CPC分类号： H01L21/82285 , H01L27/0826
摘要： An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).
摘要翻译：集成电路（100）包括高性能互补双极NPN和PNP垂直晶体管（10,20）。 NPN晶体管形成在其表面（24）被掺杂以形成PNP基极区域（28,70）的半导体衬底上。在该表面上形成一个薄膜（32,34,30），该开口（42）位于基部区域的边缘上。沿着开口的第一侧壁（78）形成第一导电间隔物（48），以在基极区域内限定PNP发射极区域（67）。第二导电间隔物（47）沿着开口的第二侧壁（76）形成以限定PNP收集区（66）。

6. 发明授权

US5920095A Short channel field effect semiconductor device and method of making 失效
标题翻译：短沟道场效应半导体器件及其制造方法
公开(公告)号：US5920095A
公开(公告)日：1999-07-06
申请号：US903080
申请日：1997-07-30
申请人： Robert Bruce Davies , Peter J. Zdebel
发明人： Robert Bruce Davies , Peter J. Zdebel
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/762 , H01L23/485 , H01L29/417 , H01L29/423 , H01L29/49 , H01L27/01
CPC分类号： H01L29/66583 , H01L21/28114 , H01L21/762 , H01L23/485 , H01L29/41766 , H01L29/41775 , H01L29/42376 , H01L29/66606 , H01L29/66636 , H01L21/2257 , H01L29/4925 , H01L29/665 , H01L2924/0002
摘要： A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a source region (44) and a drain region (45) that contact the corners (13) of the pedestal structure (16). Electrical connection to the source region (44) and the drain region (45) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).
摘要翻译：半导体器件（10）形成在覆盖半导体衬底（11）的基座结构（16）中。半导体器件（10）包括与基座结构（16）的角部（13）接触的源极区（44）和漏极区（45）。与源极区域（44）和漏极区域（45）的电连接由与基座结构（16）的侧面（12）和拐角（13）接触的导电层（28）提供。

7. 发明授权

US5712501A Graded-channel semiconductor device 失效
标题翻译：分级通道半导体器件
公开(公告)号：US5712501A
公开(公告)日：1998-01-27
申请号：US541536
申请日：1995-10-10
申请人： Robert B. Davies , Frank K. Baker , Jon J. Candelaria , Andreas A. Wild , Peter J. Zdebel
发明人： Robert B. Davies , Frank K. Baker , Jon J. Candelaria , Andreas A. Wild , Peter J. Zdebel
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66583 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7838 , H01L29/66537
摘要： A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.
摘要翻译：分级沟道半导体器件（10）包括具有主表面（12）的衬底区域（11）。源区域（13）和漏极区域（14）形成在衬底区域（11）中并且间隔开以形成沟道区域（16）。掺杂区域（18）形成在沟道区域（16）中并且与源极区域（13），漏极区域（14）和主表面（12）间隔开。掺杂区域（18）具有与沟道区域（16）相同的导电类型，但具有较高的掺杂剂浓度。与现有技术的短沟道结构相比，器件（10）表现出增强的穿通电阻和改进的性能。

8. 发明授权

US5070031A Complementary semiconductor region fabrication 失效
标题翻译：互补半导体区域制造
公开(公告)号：US5070031A
公开(公告)日：1991-12-03
申请号：US627477
申请日：1990-12-14
申请人： Peter J. Zdebel
发明人： Peter J. Zdebel
IPC分类号： H01L21/22 , H01L21/763 , H01L21/8238
CPC分类号： H01L21/763 , H01L21/2205 , H01L21/823892 , Y10S148/025
摘要： A method of forming oppositely doped semiconductor regions includes providing a first semiconductor layer of a first conductivity type and forming a second semiconductor layer of a second conductivity type on a portion of the first layer. A third semiconductor layer is formed on the second layer and the exposed portions of the first layer. The dopant concentration of the third layer is less than the dopant concentration of the second layer so that dopant of the second conductivity type diffuses from the second layer into the portion of the third layer disposed thereabove.
摘要翻译：形成相对掺杂的半导体区域的方法包括提供第一导电类型的第一半导体层，并在第一层的一部分上形成第二导电类型的第二半导体层。在第二层和第一层的暴露部分上形成第三半导体层。第三层的掺杂剂浓度小于第二层的掺杂剂浓度，使得第二导电类型的掺杂剂从第二层扩散到设置在其上的第三层的部分。

9. 发明授权

US4905070A Semiconductor device exhibiting no degradation of low current gain 失效
标题翻译：不会降低低电流增益的半导体器件
公开(公告)号：US4905070A
公开(公告)日：1990-02-27
申请号：US239879
申请日：1988-09-02
申请人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
发明人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
IPC分类号： H01L29/73 , H01L29/74
CPC分类号： H01L29/7408 , H01L29/7302
摘要： The degradation of the low current gain, which is exhibited during emitter-base reverse bias breakdown testing, is prevented by providing an emitter-base resistive shunt on the surface. This resistive shunt, preferably made of silicon nitride. utilizes surface recombination to reduce the low current gain permanently, thus a degradation is not exhibited upon testing.
摘要翻译：通过在表面上提供发射极基电阻分流来防止在发射极 - 基极反向偏压击穿测试期间显示的低电流增益的劣化。这种电阻性分流器，优选由氮化硅制成。利用表面复合来永久地降低低电流增益，从而在测试时不会出现劣化。

10. 发明授权

US08299560B2 Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same 有权
标题翻译：包括埋入绝缘层和延伸穿过其的垂直导电结构的电子器件及其形成工艺
公开(公告)号：US08299560B2
公开(公告)日：2012-10-30
申请号：US12702055
申请日：2010-02-08
申请人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
发明人： Gary H. Loechelt , Gordon M. Grivna , Peter J. Zdebel
IPC分类号： H01L21/70
CPC分类号： H01L29/66696 , H01L21/26586 , H01L21/2815 , H01L21/743 , H01L21/823475 , H01L27/1203 , H01L29/0626 , H01L29/0808 , H01L29/0821 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/1008 , H01L29/1083 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/42376 , H01L29/6625 , H01L29/66659 , H01L29/66689 , H01L29/735 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An electronic device can include a buried conductive region, a buried insulating layer over the buried conductive region, and a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a primary surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than to the primary surface. The electronic device can also include a current-carrying electrode of a first transistor, wherein the current carrying electrode is disposed along the primary surface and spaced apart from the buried conductive layer. The electronic device can also include a vertical conductive structure extending through the buried insulating layer, wherein the vertical conductive structure is electrically connected to the current-carrying electrode and the buried conductive region.
摘要翻译：电子器件可以包括掩埋导电区域，掩埋导电区域上的掩埋绝缘层和设置在掩埋绝缘层上的半导体层，其中半导体层具有主表面和相对表面，并且掩埋导电区域相对于主表面更靠近对置的表面。电子设备还可以包括第一晶体管的载流电极，其中载流电极沿着主表面设置并与掩埋的导电层间隔开。电子器件还可以包括延伸穿过掩埋绝缘层的垂直导电结构，其中垂直导电结构电连接到载流电极和掩埋导电区域。

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