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1. 发明授权

US4905070A Semiconductor device exhibiting no degradation of low current gain 失效
标题翻译：不会降低低电流增益的半导体器件
公开(公告)号：US4905070A
公开(公告)日：1990-02-27
申请号：US239879
申请日：1988-09-02
申请人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
发明人： Israel A. Lesk , Peter J. Zdebel , Han-Bin K. Liang
IPC分类号： H01L29/73 , H01L29/74
CPC分类号： H01L29/7408 , H01L29/7302
摘要： The degradation of the low current gain, which is exhibited during emitter-base reverse bias breakdown testing, is prevented by providing an emitter-base resistive shunt on the surface. This resistive shunt, preferably made of silicon nitride. utilizes surface recombination to reduce the low current gain permanently, thus a degradation is not exhibited upon testing.
摘要翻译：通过在表面上提供发射极基电阻分流来防止在发射极 - 基极反向偏压击穿测试期间显示的低电流增益的劣化。这种电阻性分流器，优选由氮化硅制成。利用表面复合来永久地降低低电流增益，从而在测试时不会出现劣化。

2. 发明授权

US5369304A Conductive diffusion barrier of titanium nitride in ohmic contact with a plurality of doped layers therefor 失效
标题翻译：氮化钛的导电扩散势垒与多个掺杂层欧姆接触
公开(公告)号：US5369304A
公开(公告)日：1994-11-29
申请号：US929232
申请日：1992-08-14
申请人： Israel A. Lesk , Francine Y. Robb , Lewis E. Terry , Frank S. d'Aragona
发明人： Israel A. Lesk , Francine Y. Robb , Lewis E. Terry , Frank S. d'Aragona
IPC分类号： H01L21/225 , H01L21/3205 , H01L23/52 , H01L29/45 , H01L29/74 , H01L23/485 , H01L29/46
CPC分类号： H01L29/45 , H01L29/452 , Y10S148/012 , Y10S257/915
摘要： A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.
摘要翻译：在半导体晶片的表面上形成多个掺杂区域（12,13,14）。氮化钛层（17）用于覆盖多个掺杂区域（12,13,14）并用于在掺杂区域（12,13,14）之间提供电连接。氮化钛层（17）基本上防止掺杂剂在随后的高温处理操作期间扩散到氮化钛（17）中并随后反掺杂掺杂区域（12,13,14）。

3. 发明授权

US5300187A Method of removing contaminants 失效
标题翻译：去除污染物的方法
公开(公告)号：US5300187A
公开(公告)日：1994-04-05
申请号：US940108
申请日：1992-09-03
申请人： Israel A. Lesk , Young Limb , Philip J. Tobin , John Franka , Paul T. Lin , Jonathan C. Dahm , Gary L. Huffman , Bich-Yen Nguyen
发明人： Israel A. Lesk , Young Limb , Philip J. Tobin , John Franka , Paul T. Lin , Jonathan C. Dahm , Gary L. Huffman , Bich-Yen Nguyen
IPC分类号： H01L21/306 , B44C1/22
CPC分类号： H01L21/02046 , Y10S438/906
摘要： Contaminants are removed from a semiconductor material by heating the semiconductor material to temperature within the range of a minimum temperature where a halogen compound will decompose to halogen atoms without the use of ultraviolet irradiation and react with contaminants present on the semiconductor material and a maximum temperature of 800.degree. C., wherein less than or equal to approximately 50 Angstroms of oxide is formed on the semiconductor material. The ambient in which the semiconductor material is heated is an ambient comprised of a nonreactive gas and a halogen compound for at least a time sufficient to remove a substantial amount of contaminants from the semiconductor material.
摘要翻译：通过将半导体材料加热到卤素化合物将分解成卤素原子的最低温度的范围内的温度而不使用紫外线照射并与存在于半导体材料上的污染物反应并且与半导体材料的最高温度 800℃，其中在半导体材料上形成小于或等于约50埃的氧化物。其中半导体材料被加热的环境是由非反应性气体和卤素化合物组成的环境，其至少足以从半导体材料中除去大量污染物的时间。

4. 发明授权

US5268326A Method of making dielectric and conductive isolated island 失效
标题翻译：制造绝缘和导电隔离岛的方法
公开(公告)号：US5268326A
公开(公告)日：1993-12-07
申请号：US951991
申请日：1992-09-28
申请人： Israel A. Lesk , Frank S. d'Aragona , Francine Y. Robb , Raymond C. Wells
发明人： Israel A. Lesk , Frank S. d'Aragona , Francine Y. Robb , Raymond C. Wells
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/76275 , H01L21/76286 , Y10S148/012 , Y10S148/135 , Y10S438/928
摘要： A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.
摘要翻译：通过提供具有第一和第二主表面的活性晶片，从第一表面延伸的掺杂区域和形成在第一表面处的沟槽来制造电介质和导电隔离岛。在第一表面和沟槽中形成导电层。然后在导电层上形成由电介质层构成的可平坦化层。把手晶片结合到可平面化层。加热有源晶片和处理晶片，使得掺杂区域沿着导电层扩散，以沿着扩散到有源晶片中的导电层形成均匀浓度的掺杂剂，以形成与所有导电层相邻的掺杂区域。然后去除活性晶片的第二表面的一部分，使得可平面化层的电介质层的至少一部分被暴露。

5. 发明授权

US5567649A Method of forming a conductive diffusion barrier 失效
标题翻译：形成导电扩散阻挡层的方法
公开(公告)号：US5567649A
公开(公告)日：1996-10-22
申请号：US519159
申请日：1995-08-24
申请人： Israel A. Lesk , Francine Y. Robb , Lewis E. Terry , Frank Secco d'Aragona
发明人： Israel A. Lesk , Francine Y. Robb , Lewis E. Terry , Frank Secco d'Aragona
IPC分类号： H01L21/225 , H01L21/3205 , H01L23/52 , H01L29/45 , H01L21/28 , H01L21/30
CPC分类号： H01L29/45 , H01L29/452 , Y10S148/012 , Y10S257/915
摘要： A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride (17) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.
摘要翻译：在半导体晶片的表面上形成多个掺杂区域（12,13,14）。氮化钛层（17）用于覆盖多个掺杂区域（12,13,14）并用于在掺杂区域（12,13,14）之间提供电连接。氮化钛层（17）基本上防止掺杂剂在随后的高温处理操作期间扩散到氮化钛（17）中并随后反掺杂掺杂区域（12,13,14）。

6. 发明授权

US4928162A Die corner design having topological configurations 失效
标题翻译：具有拓扑结构的模角设计
公开(公告)号：US4928162A
公开(公告)日：1990-05-22
申请号：US158486
申请日：1988-02-22
申请人： Israel A. Lesk , Ronald E. Thomas , George W. Hawkins , James M. Rugg
发明人： Israel A. Lesk , Ronald E. Thomas , George W. Hawkins , James M. Rugg
IPC分类号： H01L23/50 , H01L23/485 , H01L23/495
CPC分类号： H01L24/06 , H01L23/49503 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01082 , H01L2924/10253
摘要： An improved semiconductor die for plastic encapsulated semiconductor devices which impedes the inherent delamination caused by the differing expansion coefficients of the semiconductor die and plastic encapsulation. Topological configurations are processed in the die corners of the semiconductor die which are void of circuitry. The topological configurations act as barriers and slow the delamination progression. This leaves the operational circuitry unaffected for an increased time thereby increasing device lifetime.
摘要翻译：用于塑料封装的半导体器件的改进的半导体管芯，其阻止由半导体管芯和塑料封装的不同膨胀系数引起的固有分层。拓扑结构在半导体管芯的模具角处被处理，这些电路没有电路。拓扑结构作为障碍，减缓分层进程。这使得操作电路不受影响以增加时间，从而增加器件寿命。

7. 发明授权

US4837177A Method of making bipolar semiconductor device having a conductive recombination layer 失效
标题翻译：制造具有导电复合层的双极性半导体器件的方法
公开(公告)号：US4837177A
公开(公告)日：1989-06-06
申请号：US138262
申请日：1987-12-28
申请人： Israel A. Lesk , Lowell E. Clark
发明人： Israel A. Lesk , Lowell E. Clark
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/8222 , H01L27/06 , H01L29/08 , H01L29/32 , H01L29/41 , H01L29/732
CPC分类号： H01L29/32 , H01L21/74 , H01L29/0821
摘要： A semiconductor device having a conductive recombination layer. The conductive recombination layer, comprised of doped polycrystalline material, doped polycrystalline material and tungsten silicide, or tungsten silicide, is disposed between two separate semiconductor substrates which are bonded together using a polished surface on the conductive recombination layer as one of the bonding interfaces. The conductive recombination layer recombines minority carriers and thereby increases the switching speed of the device.

8. 发明授权

US4728391A Pedestal transistors and method of production thereof 失效
标题翻译：基座晶体管及其制造方法
公开(公告)号：US4728391A
公开(公告)日：1988-03-01
申请号：US48345
申请日：1987-05-11
申请人： Israel A. Lesk
发明人： Israel A. Lesk
IPC分类号： H01L21/225 , H01L21/331 , H01L21/336 , H01L21/60 , H01L21/8249 , H01L27/06 , H01L29/73 , H01L29/732 , H01L29/78 , H01L21/306 , B44C1/22 , C03C15/00 , C23F1/02
CPC分类号： H01L21/76897 , H01L21/2257 , H01L21/8249 , H01L29/66272 , H01L29/66606
摘要： The present invention describes a method of producing an MOS, bipolar and Bimos pedestal transistor wherein the source, drain, and gate metals are in place prior to the source/drain diffusion in a MOS transistor; and the emitter and base metals are in place before junction formation on the bipolar transistors. This is accomplished in MOS devices by a first blanket implantation of impurities into a first polysilicon layer during processing and a second blanket implantation into a second polysilicon layer subsequent to deposition of the metal layers. This is accomplished in bipolar devices by the above, or by blanket implantations subsequent to the deposition of the metal layers.

9. 发明授权

US4590024A Silicon deposition process 失效
标题翻译：硅沉积工艺
公开(公告)号：US4590024A
公开(公告)日：1986-05-20
申请号：US594456
申请日：1984-03-29
申请人： Israel A. Lesk , M. John Rice, Jr. , Kalluri R. Sarma
发明人： Israel A. Lesk , M. John Rice, Jr. , Kalluri R. Sarma
IPC分类号： C30B13/00
CPC分类号： C30B29/06 , C30B13/00
摘要： An improved process is disclosed for the deposition in a reactor vessel of silicon on the interior walls of the reactor vessel and for the subsequent separation of the silicon from those walls. The reactor vessel has a generally rectangular cross section and is formed of a refractory material from which the deposited silicon separates by thermal expansion shear separation during cool down of the vessel and the deposited silicon. To improve the output of the deposition system, a plurality of partitions are provided in the reactor vessel and integral with the reactor walls. These partitions act as additional deposition surfaces, increasing the number of silicon sheets deposited as well as increasing the efficiency of the chemical reaction.
摘要翻译：公开了一种改进的方法，用于沉积在反应器容器的内壁上的硅的反应器容器中，并且随后将硅与这些壁分离。反应器容器具有大致矩形的横截面，并且由耐热材料形成，沉积的硅通过在容器和沉积的硅冷却期间的热膨胀剪切分离而分离。为了提高沉积系统的输出，在反应器容器中提供多个隔板并与反应器壁成一体。这些隔板作为附加的沉积表面，增加沉积的硅片的数量以及提高化学反应的效率。

10. 发明授权

US4131488A Method of semiconductor solar energy device fabrication 失效
标题翻译：半导体太阳能装置制造方法
公开(公告)号：US4131488A
公开(公告)日：1978-12-26
申请号：US792438
申请日：1977-04-25
申请人： Israel A. Lesk , Robert A. Pryor
发明人： Israel A. Lesk , Robert A. Pryor
IPC分类号： H01L21/265 , H01L21/266 , H01L21/306 , H01L21/308 , H01L31/0216 , H01L31/0236 , H01L21/263 , H01L31/04
CPC分类号： H01L21/308 , H01L21/2652 , H01L21/266 , H01L21/30608 , H01L31/02168 , H01L31/022425 , H01L31/02363 , Y02E10/50
摘要： This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.
摘要翻译：本公开涉及一种半导体太阳能装置，其为PN型并且利用面向阳光的装置侧面上的介电抗反射涂层。用于制造该半导体器件的制造技术包括在抗反射涂层下面使用粗糙或纹理的金字塔形硅表面以增加太阳能电池效率。此外，离子注入用于在器件中形成PN结。配置在受到太阳光的器件侧的离子注入区域被配置为允许金属欧姆接触，而不会在金属触点烧结到半导体衬底期间通过掺杂区短路。在一个实施例中，介电抗反射涂层是二氧化硅和氮化硅层的复合材料。该器件被设计成允许对其P和N区域进行焊接接触，而不会短路到相反导电类型的半导体区域。

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