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1. 发明授权

US6087262A Method for manufacturing shallow trench isolation structure 有权
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6087262A
公开(公告)日：2000-07-11
申请号：US189140
申请日：1998-11-09
申请人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Gwo-Shii Yang , Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for manufacturing shallow trench isolation structure includes the steps of fabricating a self-aligned silicon nitride mask over the trench region so that a kink effect due to the misalignment of mask during a conventional mask-making process can be avoided. Moreover, the silicon nitride mask requires fewer steps and less complicated operations to construct than a conventional reverse tone mask.
摘要翻译：用于制造浅沟槽隔离结构的方法包括以下步骤：在沟槽区域上制造自对准氮化硅掩模，从而可以避免在常规掩模制造工艺期间由于掩模的未对准而产生的扭结效应。此外，与传统的反向色调掩模相比，氮化硅掩模需要更少的步骤和更少的复杂操作来构造。

2. 发明授权

US5956598A Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit 有权
标题翻译：用于在集成电路中制造具有圆角的浅沟槽隔离结构的方法
公开(公告)号：US5956598A
公开(公告)日：1999-09-21
申请号：US164736
申请日：1998-10-01
申请人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
发明人： Kuo-Tai Huang , Gwo-Shii Yang , Tri-Rung Yew , Water Lur
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A semiconductor fabrication method is provided for fabricating a shallow-trench isolation (STI) structure with a rounded corner in integrated circuits through a rapid thermal process (RTP). In the fabrication of the STI structure, a sharp corner is often undesirably formed. This sharp corner , if not eliminated, causes the occurrence of a leakage current when the resultant IC device is in operation that significantly degrades the performance of the resultant IC device. To eliminate this sharp corner , an RTP is performed at a temperature of above 1,100.degree. C., which temperature is higher than the glass transition temperature of the substrate, for about 1 to 2 minutes. The result is that the surface of the substrate is oxidized into an sacrificial oxide layer and the sharp corner is deformed into a rounded shape with a larger convex radius of curvature. This allows the problems arising from the existence of the sharp corner to be substantially eliminated. Compared to the prior art, this method not only is more simplified in process, but also allows a considerable saving in thermal budget, which makes this method more cost-effective to implement than the prior art.
摘要翻译：提供半导体制造方法，用于通过快速热处理（RTP）在集成电路中制造具有圆角的浅沟槽隔离（STI）结构。在STI结构的制造中，通常不希望地形成尖锐的拐角。如果不消除这个尖角，则当所得到的IC器件运行时会导致泄漏电流的发生，这显着降低了所得IC器件的性能。为了消除这个尖角，RTP在高于1100℃的温度下进行，该温度高于基板的玻璃化转变温度约1至2分钟。其结果是，衬底的表面被氧化成牺牲氧化物层，并且尖角变形为具有较大凸曲率半径的圆形形状。这允许基本上消除由尖角存在引起的问题。与现有技术相比，该方法不仅在过程中更简化，而且还可以大大节省热预算，这使得该方法比现有技术更具成本效益。

3. 发明授权

US06251783B1 Method of manufacturing shallow trench isolation 失效
标题翻译：制造浅沟槽隔离的方法
公开(公告)号：US06251783B1
公开(公告)日：2001-06-26
申请号：US09189847
申请日：1998-11-12
申请人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Gwo-Shii Yang , Water Lur
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.
摘要翻译：制造浅沟槽隔离结构的方法。该方法包括以下步骤：将绝缘材料沉积到衬底的沟槽中以形成绝缘层。基板具有多个活性区域，每个活性区域占据不同的区域并且具有不同的尺寸。此外，在每个有源区的顶部有一个氮化硅层。此后，然后将光致抗蚀剂层沉积在绝缘层上。接下来，将光致抗蚀剂层的一部分回蚀刻以暴露氧化物层的一部分，使得剩余的光致抗蚀剂材料在绝缘层的凹陷区域上形成覆盖层。随后，使用光致抗蚀剂覆盖层作为掩模，蚀刻绝缘层以去除暴露的氧化物层的一部分，从而在氧化物层内形成沟槽。之后，去除光致抗蚀剂覆盖层。最后，进行化学机械抛光操作以抛光绝缘层，直到暴露氮化硅层。

4. 发明授权

US06291295B1 Method of forming a storage electrode of a capacitor on an ion-implanted isolation layer 有权
标题翻译：在离子注入隔离层上形成电容器的存储电极的方法
公开(公告)号：US06291295B1
公开(公告)日：2001-09-18
申请号：US09316979
申请日：1999-05-24
申请人： Kuo-Tai Huang , Tri-Rung Yew , Water Lur
发明人： Kuo-Tai Huang , Tri-Rung Yew , Water Lur
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/02129 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/02332 , H01L21/3105 , H01L21/31625 , H01L21/76895 , H01L27/10852 , H01L28/84
摘要： A method of fabricating a capacitor. An isolation layer is formed on a substrate. An ion implantation step is performed. The isolation layer is patterned to form an opening in the isolation layer. The opening exposes a portion of the substrate. A patterned conductive layer is formed on the isolation layer to fill the opening. A hemispherical grained silicon layer is performed on the conductive layer. In addition, the step order of the ion implantation step can be changed. The ion implantation can also be performed after the opening is formed.
摘要翻译：一种制造电容器的方法。在基板上形成隔离层。执行离子注入步骤。隔离层被图案化以在隔离层中形成开口。开口露出基底的一部分。在隔离层上形成图案化的导电层以填充开口。在导电层上进行半球状的硅层。此外，可以改变离子注入步骤的步骤顺序。离子注入也可以在开口形成之后进行。

5. 发明授权

US06251769B1 Method of manufacturing contact pad 失效
标题翻译：制造接触垫的方法
公开(公告)号：US06251769B1
公开(公告)日：2001-06-26
申请号：US09347180
申请日：1999-07-02
申请人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
发明人： Tri-Rung Yew , Kuo-Tai Huang , Water Lur
IPC分类号： H01L214763
CPC分类号： H01L24/03 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76814 , H01L21/76879 , H01L21/76895 , H01L21/76897 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01033 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer.
摘要翻译：一种制造接触垫的方法。提供其中形成有源极/漏极区的衬底。介电层形成在衬底上。在电介质层中形成开口并使源极/漏极区域露出。执行选择性外延工艺以在开口中形成接触焊盘，其中接触焊盘的顶部延伸到介电层的表面上。

6. 发明授权

US06479344B2 Method of fabricating DRAM capacitor 失效
标题翻译：制造DRAM电容的方法
公开(公告)号：US06479344B2
公开(公告)日：2002-11-12
申请号：US09542715
申请日：2000-04-04
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3211 , H01L27/10852 , H01L28/55
摘要： A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.
摘要翻译：制造DRAM电容器的方法在形成电容器的过程中使用氮化钨。电容器的结构简单，易于执行。此外，本发明提供了一种形成氮化钨的方法，包括将氮气注入到硅化钨层中的步骤以及在氨气下执行快速热处理以在硅化钨层的表面上形成氮化钨层的步骤。制造DRAM电容器的方法包括在从掺杂多晶硅形成小于电容器的底部电极的部分之后形成硅化钨层，并在氮化钨层的表面上形成氮化钨。

7. 发明授权

US06221712B1 Method for fabricating gate oxide layer 失效
标题翻译：栅极氧化层的制造方法
公开(公告)号：US06221712B1
公开(公告)日：2001-04-24
申请号：US09385805
申请日：1999-08-30
申请人： Kuo-Tai Huang , Michael W C Huang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Michael W C Huang , Tri-Rung Yew
IPC分类号： B32B1900
CPC分类号： H01L21/28194 , C23C16/405 , H01L21/28088 , H01L21/31604 , H01L29/4966 , H01L29/517
摘要： A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.
摘要翻译：一种用于制造栅极结构的方法。该方法包括提供衬底，随后在衬底的表面上形成氮化物区域。使用钽（Ta）基有机化合物和作为前体的钛（Ti）基有机化合物，进行有机金属化学气相沉积（OMCVD），从而在衬底上形成Ta2-xTixO5电介质层。然后依次在Ta2-xTixO5电介质层上形成阻挡层，导电层和抗反射（AR）层。随后，将AR层，导电层，阻挡层和Ta2-xTixO5电介质层定义为在氮化物区域的衬底上形成栅极结构。在这种情况下，Ta类有机化合物可以包括Ta-醇盐化合物，而Ti基有机化合物可以包括Ti-醇盐化合物或Ti-酰胺化合物。

8. 发明授权

US6037206A Method of fabricating a capacitor of a dynamic random access memory 失效
标题翻译：制造动态随机存取存储器的电容器的方法
公开(公告)号：US6037206A
公开(公告)日：2000-03-14
申请号：US080116
申请日：1998-05-15
申请人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the capacitor is formed over a substrate and is electrically coupled to an interchangeable source/drain region through a contact window penetrating an insulating layer. Then performing etching process on the lower conductive layer so as to form a fence-like plate with a higher height than a thickness of the lower conductive layer and adhere to the lower conductive layer. Next a media conductive layer is formed over the lower conductive layer and the fence-like plate. Then the technology of etching back is utilized to round the sharp area on the tip of the fence-like plate. The lower conductive layer and the media conductive layer are electrically coupled together as a lower electrode. Then, a dielectric thin film is formed over the media conductive layer and an upper electrode is formed over the dielectric thin film. Therefore, a MIM capacitor according to the preferred embodiment of the invention is formed.
摘要翻译：一种用于制造DRAM电容器的方法包括：电容器的下导电层形成在衬底上，并通过穿透绝缘层的接触窗电耦合到可互换的源/漏区。然后对下导电层进行蚀刻处理，以形成具有比下导电层的厚度高的高度的栅栏状的板，并粘附到下导电层。接下来，在下导电层和栅栏状板上形成介质导电层。然后，利用蚀刻技术来围绕栅栏状板的尖端上的尖锐区域。下导电层和介质导电层作为下电极电耦合在一起。然后，在介质导电层上形成电介质薄膜，在电介质薄膜上方形成上电极。因此，形成根据本发明的优选实施例的MIM电容器。

9. 发明授权

US06235606B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06235606B1
公开(公告)日：2001-05-22
申请号：US09225031
申请日：1999-01-04
申请人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76224
摘要： A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.
摘要翻译：一种制造浅沟槽隔离的方法。在衬底上形成衬垫氧化物层和掩模层。将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。在由沟槽暴露的衬底上形成衬里氧化物层。在衬底上形成隔离层以覆盖衬里氧化物层。隔离层与沟槽保形。在衬底上形成氧化物层以填充沟槽。除去氧化物层和隔离层的一部分直到掩模层露出。去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

10. 发明授权

US06078492A Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall 失效
标题翻译：具有具有倾斜侧壁的自对准接触窗的半导体器件中的电容器的结构
公开(公告)号：US06078492A
公开(公告)日：2000-06-20
申请号：US128364
申请日：1998-08-03
申请人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
发明人： Kuo-Tai Huang , Wen-Yi Hsieh , Tri-Rung Yew
IPC分类号： H01L27/108 , H01L21/02 , H01L21/8242 , H01G4/30 , H01G4/008
CPC分类号： H01L27/10852 , H01L28/82
摘要： A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a dielectric thin film with a material having high dielectric constant is over the lower electrode. Then, an upper electrode is over the dielectric thin film to complete a capacitor, which has a structure of metal insulator metal with a shape like the PSACW.
摘要翻译：电容器的结构包括两个栅极和在衬底上的常用源极/漏极区域。然后，凹陷的自对准接触窗口（PSACW）部分地暴露常用的源极/漏极区域。然后电容器的胶/阻挡层和下电极在PSACW之上。然后，具有高介电常数的材料的电介质薄膜在下电极之上。然后，上电极在电介质薄膜的上方，以完成电容器，该电容器具有类似于PSACW形状的金属绝缘体金属的结构。

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