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1. 发明授权

US09293606B2 Semiconductor device with seal ring with embedded decoupling capacitor 有权
标题翻译：带封装环的半导体器件带有去耦电容
公开(公告)号：US09293606B2
公开(公告)日：2016-03-22
申请号：US13296410
申请日：2011-11-15
申请人： Kuo-Ji Chen , Wei Yu Ma , Ta-Pen Guo , Hsien-Wei Chen , Hao-Yi Tsai
发明人： Kuo-Ji Chen , Wei Yu Ma , Ta-Pen Guo , Hsien-Wei Chen , Hao-Yi Tsai
IPC分类号： H01L29/93 , H01L29/94 , H01L23/522 , H01L23/528 , H01L23/58 , H01L27/06 , H01L27/08 , H01L49/02
CPC分类号： H01L29/93 , H01L23/5223 , H01L23/5286 , H01L23/585 , H01L27/0629 , H01L27/0805 , H01L28/60 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A seal ring for semiconductor devices is provided with embedded decoupling capacitors. The seal ring peripherally surrounds an integrated circuit chip in a seal ring area. The at least one embedded decoupling capacitor may include MOS capacitors, varactors, MOM capacitors and interdigitized capacitors with multiple capacitor plates coupled together. The opposed capacitor plates are coupled to different potentials and may advantageously be coupled to Vdd and Vss.
摘要翻译：用于半导体器件的密封环设置有嵌入式去耦电容器。密封环外围围绕密封环区域中的集成电路芯片。至少一个嵌入式去耦电容器可以包括MOS电容器，变容二极管，MOM电容器和具有多个电容器板耦合在一起的叉指电容器。相对的电容器板耦合到不同的电位，并且可以有利地耦合到Vdd和Vss。

2. 发明授权

US09117677B2 Semiconductor integrated circuit having a resistor and method of forming the same 有权
标题翻译：具有电阻器的半导体集成电路及其形成方法
公开(公告)号：US09117677B2
公开(公告)日：2015-08-25
申请号：US13272389
申请日：2011-10-13
申请人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
发明人： Wei Yu Ma , Kuo-Ji Chen , Fang-Tsun Chu , Ta-Pen Guo
IPC分类号： H01L27/06 , H01L21/768 , H01L27/02 , H01L23/522
CPC分类号： H01L27/0266 , H01L21/76895 , H01L23/5228 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.
摘要翻译：本申请公开了一种半导体集成电路，包括其上形成有电气器件的衬底，形成在衬底上的局部互连层，以及形成在局部互连层上的全局互连层。局部互连层具有第一组导电结构，其布置成在各个电气设备之间，电气设备及其相邻的电气设备之一中，或垂直设备和全局互连层之间电连接。第一组导电结构中的至少一个被配置为具有大于50欧姆的电阻值。全局互连层具有布置成经由第一组导电结构电连接电器件的第二组导电结构。

3. 发明授权

US5406138A Programmable interconnect architecture using fewer storage cells than switches 失效
标题翻译：可编程互连架构比开关使用更少的存储单元
公开(公告)号：US5406138A
公开(公告)日：1995-04-11
申请号：US51449
申请日：1993-04-19
申请人： Adi Srinivasan , Ta-Pen Guo
发明人： Adi Srinivasan , Ta-Pen Guo
IPC分类号： H03K17/00 , H03K17/693 , H03K19/173 , H03K19/177 , H03K19/094
CPC分类号： H03K19/1776 , H03K17/693 , H03K19/17704 , H03K19/17736
摘要： A first user re-programmable interconnect architecture is provided wherein N switching elements are connected between selected interconnect conductors. The switching elements are controlled by M active storage elements, where M
摘要翻译：提供了第一用户可重新编程的互连架构，其中N个开关元件连接在选定的互连导体之间。开关元件由M个主动存储元件控制，其中M

4. 发明授权

US5341267A Structures for electrostatic discharge protection of electrical and other components 失效
标题翻译：电气和其他部件的静电放电保护结构
公开(公告)号：US5341267A
公开(公告)日：1994-08-23
申请号：US763964
申请日：1991-09-23
申请人： Ralph G. Whitten , Ta-Pen Guo , Amr Mohsen , Alan E. Comer
发明人： Ralph G. Whitten , Ta-Pen Guo , Amr Mohsen , Alan E. Comer
IPC分类号： H01L23/60 , H02H9/00 , H01H37/76
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/3011
摘要： A first passive ESD protection device for an electronic component in a microcircuit includes a fuse element shunting the component to be protected and includes a passive programming path from the outside of the microcircuit to the fuse element. A second passive ESD protection device is deactivatable and reactivatable and includes a first fuse element shunted by a second fuse element in series with a first antifuse element. Shunting the second fuse element with a third fuse element in series with a second antifuse element permits a second deactivation and reactivation to be performed. Additional deactivation/reactivation cycles may be permitted by providing additional series combinations of fuse elements and antifuse elements shunting the preceding fuse element. Combinations of the passive protection device and dual elements comprise ESD protection schemes which may be deactivated and activated multiple times.
摘要翻译：用于微电路中的电子部件的第一无源ESD保护装置包括分流待保护的部件的熔丝元件，并且包括从微电路的外部到熔丝元件的无源编程路径。第二无源ESD保护装置是可去激活的并且可再生的，并且包括由与第一反熔丝元件串联的第二熔丝元件分流的第一熔丝元件。利用与第二反熔丝元件串联的第三熔丝元件来分流第二熔丝元件允许执行第二失活和重新激活。可以通过提供分流前一个熔丝元件的熔丝元件和反熔丝元件的附加串联组合来允许附加的去激活/重新激活循环。被动保护装置和双重元件的组合包括ESD保护方案，其可以被多次停用和激活。

5. 发明授权

US09312260B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US09312260B2
公开(公告)日：2016-04-12
申请号：US13086186
申请日：2011-04-13
申请人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
发明人： Ali Keshavarzi , Ta-Pen Guo , Helen Shu-Hui Chang , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Shu-Min Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L29/76 , H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L29/0649 , H01L29/4238 , H01L29/495 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域分离。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属结构与第一源区电耦合。第二金属结构与第二漏区电耦合。第三金属结构设置在第一和第二金属结构之上并与第一和第二金属结构电耦合。第一金属结构体的宽度基本上等于或大于第三金属结构体的宽度。

6. 发明授权

US07940108B1 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US07940108B1
公开(公告)日：2011-05-10
申请号：US12692884
申请日：2010-01-25
申请人： Guang-Cheng Wang , Ta-Pen Guo
发明人： Guang-Cheng Wang , Ta-Pen Guo
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A circuit, includes first, second, and third inverters. The first inverter has a first input coupled to a first port and a first output coupled to a second port. The second inverter has a second input coupled to the second port and a second output coupled to the first port. The third inverter has a third input coupled to the first port through a first capacitor and to a third port. The third inverter has an output coupled to the second port through a second capacitor. The circuit receives a signal having a voltage between a first voltage potential and a second voltage potential and in response outputs a signal having a voltage between the second voltage potential and a third voltage potential. The third voltage potential is higher than the first and second voltage potentials with respect to ground.
摘要翻译：电路包括第一，第二和第三逆变器。第一反相器具有耦合到第一端口的第一输入端和耦合到第二端口的第一输出端。第二反相器具有耦合到第二端口的第二输入端和耦合到第一端口的第二输出端。第三反相器具有通过第一电容器耦合到第一端口的第三输入端和第三端口。第三反相器具有通过第二电容器耦合到第二端口的输出。电路接收具有第一电压电位和第二电压电位之间的电压的信号，并且响应于输出具有在第二电压电位和第三电压电位之间的电压的信号。第三电压电位高于相对于地的第一和第二电压电位。

7. 发明授权

US07932566B2 Structure and system of mixing poly pitch cell design under default poly pitch design rules 有权
标题翻译：在默认聚沥青设计规则下混合聚沥青单元设计的结构和系统
公开(公告)号：US07932566B2
公开(公告)日：2011-04-26
申请号：US12347628
申请日：2008-12-31
申请人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
发明人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
IPC分类号： H01L25/00
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11803
摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.
摘要翻译：提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。

8. 发明申请

US20100127333A1 NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
标题翻译：性能增强的新型布局架构
公开(公告)号：US20100127333A1
公开(公告)日：2010-05-27
申请号：US12276172
申请日：2008-11-21
申请人： Yung-Chin Hou , Ta-Pen Guo , Harry Chuang , Carlos H. Diaz , Lee-Chung Lu , Li-Chun Tien , Oscar M. K. Law , Chih-Chiang Chang , Chun-Hui Tai , Jonathan Lee
发明人： Yung-Chin Hou , Ta-Pen Guo , Harry Chuang , Carlos H. Diaz , Lee-Chung Lu , Li-Chun Tien , Oscar M. K. Law , Chih-Chiang Chang , Chun-Hui Tai , Jonathan Lee
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823481
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.
摘要翻译：本发明提供集成电路。集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET）以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。

9. 发明授权

US5400294A Memory cell with user-selectable logic state on power-up 失效
标题翻译：上电时用户可选逻辑状态的存储单元
公开(公告)号：US5400294A
公开(公告)日：1995-03-21
申请号：US162585
申请日：1993-12-06
申请人： Adi Srinivasan , Ta-Pen Guo
发明人： Adi Srinivasan , Ta-Pen Guo
IPC分类号： G11C7/20 , G11C7/22 , G11C11/40
CPC分类号： G11C7/20 , G11C7/22
摘要： Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V.sub.CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V.sub.CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and bit lines and V.sub.CC. During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V.sub.CC by the P-Channel pullup transistors. When V.sub.CC reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V.sub.CC, thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V.sub.CC final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V.sub.CC and the bit lines and V.sub.CC.
摘要翻译：用于在上电时将存储器单元强制为用户选择的逻辑电平的装置包括用于提供在芯片上电期间使用的两个信号PWRUP和PWRUPB的电路。上电时，当VCC从0伏升至3.5伏时，PWRUP信号遵循VCC，PWRUPB信号保持0伏。 PWRUP和PWRUPB信号分别用于驱动P沟道和N沟道MOS晶体管的栅极，包括连接在字线驱动电路和驱动与存储单元相关联的字线和位线驱动电路之间的通路。此外，PWRUPB信号用于驱动连接在字线与VCC和位线和VCC之间的P沟道MOS上拉晶体管。在上电期间，禁止通过门，将字线和位线与驱动器断开。字线和位线被迫通过P沟道上拉晶体管跟随VCC的上升。当VCC达到所需值时，PWRUP信号变为0伏，PWRUPB信号变为VCC，从而打开通过门，将字线和位线驱动电路连接到字线和位线。 VCC最终PWRUPB信号关闭连接在字线和VCC与位线和VCC之间的P沟道MOS上拉晶体管。

10. 发明授权

US08362573B2 Integrated circuits and manufacturing methods thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US08362573B2
公开(公告)日：2013-01-29
申请号：US12787966
申请日：2010-05-26
申请人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
发明人： Chung-Cheng Wu , Ali Keshavarzi , Ka Hing Fung , Ta-Pen Guo , Jiann-Tyng Tzeng , Yen-Ming Chen , Shyue-Shyh Lin , Shyh-Wei Wang , Sheng-Jier Yang , Hsiang-Jen Tseng , David B. Scott , Min Cao
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L27/0207 , H01L27/092 , H01L29/7848 , H01L2224/16225
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is spaced from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. The first metallic layer is electrically coupled with the first source region. The first metallic layer and the first diffusion area overlap with a first distance. A second metallic layer is electrically coupled with the first drain region and the second drain region. The second metallic layer and the first diffusion area overlap with a second distance. The first distance is larger than the second distance.
摘要翻译：集成电路包括用于第一类型晶体管的第一扩散区域。第一类型晶体管包括第一漏极区域和第一源极区域。用于第二类型晶体管的第二扩散区域与第一扩散区域间隔开。第二类型晶体管包括第二漏极区域和第二源极区域。栅电极在布线方向上连续延伸穿过第一扩散区域和第二扩散区域。第一金属层与第一源区电耦合。第一金属层和第一扩散区域与第一距离重叠。第二金属层与第一漏极区域和第二漏极区域电耦合。第二金属层和第一扩散区域与第二距离重叠。第一距离大于第二距离。

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