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    • 2. 发明申请
    • Self-aligned top-gate thin film transistors and method for fabricating same
    • 自对准顶栅薄膜晶体管及其制造方法
    • US20120018718A1
    • 2012-01-26
    • US12927835
    • 2010-11-26
    • Hsiao-Wen ZanWei-Tsung ChenCheng-Wei ChouChuang-Chuang Tsai
    • Hsiao-Wen ZanWei-Tsung ChenCheng-Wei ChouChuang-Chuang Tsai
    • H01L29/12H01L21/04
    • H01L29/7869H01L29/42384H01L29/66969
    • A self-aligned top-gate thin film transistor and a fabrication method thereof. The method includes preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer includes first and second connecting regions that are not covered by the dielectric layer and the metallic layer thereon respectively, the first and second connecting regions having a property of a conductor after undergone a heating process or an ultraviolet irradiation; and a source electrode and a drain electrode formed on the substrate and connected to the first and second connecting regions, respectively. Therefore, the contact resistance of the first and second connecting regions can be reduced without the process of ion dopants as required by prior art techniques, thereby simplifying the manufacturing process. Also, the source electrode and the drain electrode can be exactly relocated and further increase performance of the device.
    • 一种自对准顶栅薄膜晶体管及其制造方法。 该方法包括制备其上依次形成有氧化物半导体层,电介质层和金属层的衬底,其中氧化物半导体层包括分别不被电介质层和金属层覆盖的第一和第二连接区域, 所述第一和第二连接区域在进行加热处理或紫外线照射之后具有导体的性质; 以及源极电极和漏电极,分别形成在所述基板上并连接到所述第一和第二连接区域。 因此,不需要现有技术所要求的离子掺杂剂的处理,可以减少第一和第二连接区域的接触电阻,从而简化了制造工艺。 此外,源电极和漏电极可以精确地定位并进一步提高器件的性能。