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1. 发明申请

US20130117641A1 METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE 有权
标题翻译：用于存储器件中的错误管理的方法和系统
公开(公告)号：US20130117641A1
公开(公告)日：2013-05-09
申请号：US13619452
申请日：2012-09-14
申请人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
发明人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1016
摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
摘要翻译：一种用于存储器件中的错误管理的方法和系统。在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

2. 发明授权

US09158616B2 Method and system for error management in a memory device 有权
标题翻译：存储器件中错误管理的方法和系统
公开(公告)号：US09158616B2
公开(公告)日：2015-10-13
申请号：US13619452
申请日：2012-09-14
申请人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
发明人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/10 , G06F11/1016
摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
摘要翻译：一种用于存储器件中的错误管理的方法和系统。在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

3. 发明授权

US08862973B2 Method and system for error management in a memory device 有权
标题翻译：存储器件中错误管理的方法和系统
公开(公告)号：US08862973B2
公开(公告)日：2014-10-14
申请号：US12634286
申请日：2009-12-09
申请人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
发明人： Kuljit S. Bains , David J. Zimmerman , Dennis W. Brzezinski , Michael Williams , John B. Halbert
IPC分类号： G06F11/00
CPC分类号： G06F11/1016
摘要： A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command.
摘要翻译：一种用于存储器件中的错误管理的方法和系统。在本发明的一个实施例中，存储器设备可以处理命令和寻址奇偶校验错误和循环冗余校验错误。在本发明的一个实施例中，存储器可以通过确定接收到的命令的命令位或地址位是否具有任何奇偶校验错误来检测所接收的命令是否具有任何奇偶校验错误。如果检测到接收到的命令中的奇偶校验错误或循环冗余校验错误，则触发错误处理机制以从错误命令中恢复。

4. 发明授权

US08196009B2 Systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code 有权
标题翻译：使用共享错误位代码在公共帧中传输数据和数据屏蔽位的系统，方法和装置
公开(公告)号：US08196009B2
公开(公告)日：2012-06-05
申请号：US12141339
申请日：2008-06-18
申请人： Kuljit S. Bains , Dennis W. Brzezinski
发明人： Kuljit S. Bains , Dennis W. Brzezinski
IPC分类号： H03M13/00
CPC分类号： G11C7/1006 , G06F11/1004 , G11C7/1045 , G11C7/1051 , G11C7/1069
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame.
摘要翻译：本发明的实施例一般涉及用共享错误位代码传送公共帧中的数据和数据掩码位的系统，方法和装置。存储器系统使用数据帧在主机和存储器件之间传输数据。在一些情况下，系统还可以传送数据帧中的一个或多个数据屏蔽位（而不是通过单独的位通道）。系统可以生成错误比特校验和（例如循环冗余码或CRC）来覆盖数据比特和数据掩码比特。在一些实施例中，数据位，数据屏蔽位和校验和位在公共帧中传送。

5. 发明申请

US20090319877A1 SYSTEMS, METHODS, AND APPARATUSES TO TRANSFER DATA AND DATA MASK BITS IN A COMMON FRAME WITH A SHARED ERROR BIT CODE 有权
标题翻译：用共享错误位代码传输数据和数据掩码位置的系统，方法和设备
公开(公告)号：US20090319877A1
公开(公告)日：2009-12-24
申请号：US12141339
申请日：2008-06-18
申请人： Kuljit S. Bains , Dennis W. Brzezinski
发明人： Kuljit S. Bains , Dennis W. Brzezinski
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G11C7/1006 , G06F11/1004 , G11C7/1045 , G11C7/1051 , G11C7/1069
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit code. A memory system uses data frames to transfer data between a host and a memory device. In some cases, the system may also transfer one or more data mask bits in a data frame (rather than via a separate bit lane). The system may generate an error bit checksum (such as a cyclic redundancy code or CRC) to cover the data bits and the data mask bits. In some embodiments, the data bits, data mask bits, and checksum bits are transferred in a common frame.
摘要翻译：本发明的实施例一般涉及用共享错误位代码传送公共帧中的数据和数据掩码位的系统，方法和装置。存储器系统使用数据帧在主机和存储器件之间传输数据。在一些情况下，系统还可以传送数据帧中的一个或多个数据屏蔽位（而不是通过单独的位通道）。系统可以生成错误比特校验和（例如循环冗余码或CRC）来覆盖数据比特和数据掩码比特。在一些实施例中，数据位，数据屏蔽位和校验和位在公共帧中传送。

6. 发明申请

US20130097371A1 DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL 有权
标题翻译：为存储通道上的最后一个存储器缓冲区禁用外部驱动器
公开(公告)号：US20130097371A1
公开(公告)日：2013-04-18
申请号：US13692355
申请日：2012-12-03
申请人： Warren Morrow , Pete Vogt , Dennis W. Brzezinski
发明人： Warren Morrow , Pete Vogt , Dennis W. Brzezinski
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
摘要翻译：使用多个位通道的存储装置和方法可以重定向在位通道上的一个或多个信号。存储器可以包括具有多个位通道的重新驱动电路，存储器件或接口以及耦合在多个位通道和存储器件或接口之间的故障切换电路。

7. 发明授权

US08990506B2 Replacing cache lines in a cache memory based at least in part on cache coherency state information 有权
标题翻译：至少部分地基于高速缓存一致性状态信息来替换缓存存储器中的高速缓存行
公开(公告)号：US08990506B2
公开(公告)日：2015-03-24
申请号：US12639191
申请日：2009-12-16
申请人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
发明人： Naveen Cherukuri , Dennis W. Brzezinski , Ioannis T. Schoinas , Anahita Shayesteh , Akhilesh Kumar , Mani Azimi
IPC分类号： G06F12/00 , G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/084 , G06F12/126
摘要： In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括高速缓存存储器，其包括高速缓存行，每个高速缓存行具有包括状态部分的标签字段，该状态部分存储存储在该行中的数据的高速缓存一致性状态，以及权重部分，用于存储对应于数据。在各种实现中，权重可以基于高速缓存一致性状态和数据的使用的新近。描述和要求保护其他实施例。

8. 发明授权

US08286039B2 Disabling outbound drivers for a last memory buffer on a memory channel 失效
公开(公告)号：US08286039B2
公开(公告)日：2012-10-09
申请号：US13340552
申请日：2011-12-29
申请人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
发明人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
IPC分类号： G01R31/28
CPC分类号： G06F12/00 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

9. 发明授权

US08250435B2 Memory error detection and/or correction 有权
标题翻译：存储器错误检测和/或校正
公开(公告)号：US08250435B2
公开(公告)日：2012-08-21
申请号：US12559953
申请日：2009-09-15
申请人： Robert G. Blankenship , Dennis W. Brzezinski , Edwin F. Mendez Valverde
发明人： Robert G. Blankenship , Dennis W. Brzezinski , Edwin F. Mendez Valverde
IPC分类号： H03M13/00
CPC分类号： G06F11/1004
摘要： An embodiment may include circuitry that may detect and/or correct at least one error in a data codeword that may include a data word, cyclical redundancy check (CRC) word, and parity word. The circuitry may select whether a portion of the CRC word indicates whether only a single processor has accessed the data word. The data word, CRC word, and the parity word may be accessible in respective distinct memory device sets that each may include one or more respective memory devices. If the circuitry detects, based at least in part upon the data codeword and CRC word, a CRC error, and the at least one error includes fewer than a first predetermined number of errors, the circuitry may determine in which of the one or more respective memory devices in the memory device sets the at least one error resides and may correct the at least one error.
摘要翻译：实施例可以包括可以检测和/或校正可包括数据字，循环冗余校验（CRC）字和奇偶校验字的数据码字中的至少一个错误的电路。电路可以选择CRC字的一部分是否指示单个处理器是否已经访问了数据字。数据字，CRC字和奇偶校验字可以在各自不同的存储器件组中可访问，每个不同的存储器件集合可以包括一个或多个相应的存储器件。如果电路至少部分地基于数据码字和CRC字来检测CRC错误，并且该至少一个错误包括少于第一预定数量的错误，则电路可以确定在一个或多个相应的存储器设备中的存储器设备设置至少一个错误，并且可以校正至少一个错误。

10. 发明授权

US08020056B2 Memory channel with bit lane fail-over 有权
标题翻译：具有位线故障切换的内存通道
公开(公告)号：US08020056B2
公开(公告)日：2011-09-13
申请号：US12836953
申请日：2010-07-15
申请人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
发明人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
IPC分类号： G11C29/00
CPC分类号： G06F12/00 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
摘要翻译：使用多个位通道的存储装置和方法可以重定向在位通道上的一个或多个信号。存储器可以包括具有多个位通道的重新驱动电路，存储器件或接口以及耦合在多个位通道和存储器件或接口之间的故障切换电路。

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