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    • 3. 发明授权
    • Multi-chip package reducing power-up peak current
    • 多芯片封装降低上电峰值电流
    • US07746719B2
    • 2010-06-29
    • US12177323
    • 2008-07-22
    • Sang-Gu Kang
    • Sang-Gu Kang
    • G11C17/18
    • G11C7/20G11C5/147
    • Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips.
    • 公开了具有多个存储器芯片的多芯片封装。 每个存储器芯片包括存储电子熔丝数据的存储单元阵列,响应于读取信号读取电子熔丝数据的读出控制电路,接收第一控制信号的第一内部焊盘,产生读取的读出控制器的读出控制器 信号以定义读周期,并产生跟随读周期的第二控制信号,以及第二内部焊盘接收第二控制信号,其中多个存储器芯片连接串联,每个相应的读出控制电路和读 - 多个存储器芯片中的每一个的输出控制器协作以实现跨多个存储器芯片的电子熔丝数据的顺序读取。
    • 4. 发明授权
    • Substrate test probing equipment having forcing part for test head and force-receiving pattern for probe card and methods of using the same
    • 具有强制部分用于探针卡的测试头和受力图案的基板测试探测设备及其使用方法
    • US07701235B2
    • 2010-04-20
    • US12098778
    • 2008-04-07
    • Chang-Hyun ChoJoon-Yeon KimSang-Gu KangSung-Mo KangSang-Kyu Yoo
    • Chang-Hyun ChoJoon-Yeon KimSang-Gu KangSung-Mo KangSang-Kyu Yoo
    • G01R31/02
    • G01R31/2889G01R31/2891
    • Substrate test probing equipment having a force-receiving pattern for a probe card and a forcing part for a test head, and methods of using the same, in which with the force-receiving pattern for the probe card and the forcing part for the test head, thermal expansion and contraction of the probe card can be suppressed when the semiconductor substrate is being tested at high and low temperatures. To this end, to substrate test probing equipment having a substrate mover, a probe card, and a test head is prepared, in which the test head has a forcing part and the probe card has a force-receiving plate. A semiconductor substrate is placed on the substrate mover to be electrically connected with the probe card. The semiconductor substrate is electrically tested by the probe card and the test head. When the semiconductor substrate is being tested, the forcing part of the test head is brought into contact with the force-receiving pattern of the probe card.
    • 具有用于探针卡的力接收图案和用于测试头的强制部件的基板测试探测设备及其使用方法,其中用于探针卡的受力图案和用于测试头的强制部件 当在高温和低温下测试半导体衬底时,可以抑制探针卡的热膨胀和收缩。 为此,制备具有基板移动器,探针卡和测试头的基板测试探测设备,其中测试头具有强制部分,探针卡具有受力板。 将半导体衬底放置在衬底移动器上以与探针卡电连接。 半导体衬底由探针卡和测试头电测试。 当半导体衬底被测试时,测试头的强制部分与探针卡的受力图案接触。
    • 5. 发明授权
    • Flash memory device using program data cache and programming method thereof
    • 闪存设备使用程序数据缓存及其编程方法
    • US07561467B2
    • 2009-07-14
    • US11657697
    • 2007-01-25
    • Dong-Ku KangYoung-Ho LimSang-Gu Kang
    • Dong-Ku KangYoung-Ho LimSang-Gu Kang
    • G11C11/34
    • G11C16/3454G11C11/5628G11C2211/5621G11C2211/5642G11C2211/5643
    • A method is for programming a flash memory device which includes a plurality of memory cells storing multi-bit data representing one of a plurality of states. The method includes programming the multi-bit data into selected memory cells of the plurality of memory cells, the programming including a first verify-reading operation performed by a first verifying voltage, determining whether to execute a reprogramming operation for each of the selected memory cells, and reprogramming the selected memory cells in accordance with the determination. The reprogramming of the selected memory cells includes a second verify-reading operation performed by a second verifying voltage, the second verifying voltage being higher than the first verifying voltage.
    • 一种用于对闪速存储器件进行编程的方法,该闪存器件包括存储表示多种状态之一的多位数据的多个存储器单元。 该方法包括将多位数据编程到多个存储单元的选定存储单元中,该程序包括由第一验证电压执行的第一验证读取操作,确定是否对所选存储单元中的每一个执行重编程操作 ,并且根据该确定重新编程所选择的存储单元。 所选择的存储单元的重新编程包括由第二验证电压执行的第二验证读取操作,第二验证电压高于第一验证电压。
    • 6. 发明申请
    • Flash memory devices and programming methods for the same
    • 闪存设备和编程方法相同
    • US20080068883A1
    • 2008-03-20
    • US11651521
    • 2007-01-10
    • Sang-Gu KangYoung-Ho Lim
    • Sang-Gu KangYoung-Ho Lim
    • G11C16/04
    • G11C11/5628
    • Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.
    • 提供闪存设备及其编程方法。 闪速存储器件包括存储多位数据的多个存储单元,该多位数据表示第一至第四状态中的至少一个,并且包括最高有效位和最低有效位。 该方法包括根据最低有效位将多个存储器单元编程为临时状态,并根据最高有效位将第一至暂态状态的多个存储单元编程为第二至第四状态。 将多个存储器单元编程为第二至第四状态包括在一个编程操作周期期间至少部分地将多个存储器单元编程为至少两个状态。