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1. 发明授权

US09236267B2 Cut-mask patterning process for fin-like field effect transistor (FinFET) device 有权
标题翻译：鳍状场效应晶体管（FinFET）器件的切割掩模图案化工艺
公开(公告)号：US09236267B2
公开(公告)日：2016-01-12
申请号：US13369818
申请日：2012-02-09
申请人： Ho Wei De , Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
发明人： Ho Wei De , Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
IPC分类号： H01L21/308 , H01L21/84 , H01L27/12
CPC分类号： G03F1/38 , G03F7/70466 , H01L21/3086 , H01L21/3088 , H01L21/845 , H01L27/1211
摘要： A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
摘要翻译：用于图案化非矩形图案中的多个特征的方法，例如在集成电路器件上，包括提供包括具有多个细长突起的表面的基底，所述细长突起沿第一方向延伸。第一层形成在多个细长突起的表面上方和上方，并用端部切割掩模图案化。末端切割掩模包括两个几乎相邻的图案，其具有定位和配置的次分辨率特征，使得当第一层上的所得图案包括两个近似相邻的图案时，以及其间的连接。该方法还包括使用第一层上的图案切割细长突起的端部。

2. 发明申请

US20130244434A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130244434A1
公开(公告)日：2013-09-19
申请号：US13418589
申请日：2012-03-13
申请人： Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
发明人： Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
IPC分类号： H01L21/312
CPC分类号： H01L21/0332 , H01L21/31058 , H01L21/31144 , H01L21/76802 , H01L21/76819 , H01L21/76837
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成多个电路器件。该方法包括在衬底上形成有机层。有机层形成在多个电路装置上。该方法包括抛光有机层以使有机层的表面平坦化。有机层在抛光之前不需要进行热处理。有机材料在抛光期间是未交联的。该方法包括在有机层的平坦化表面上沉积LT膜。沉积在小于约150摄氏度的温度下进行。也可以不使用旋涂法进行沉积。该方法包括在LT膜上形成图案化的光致抗蚀剂层。

3. 发明申请

US20130210232A1 CUT-MASK PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE 有权
标题翻译：晶体效应晶体管（FINFET）器件的切割掩模处理
公开(公告)号：US20130210232A1
公开(公告)日：2013-08-15
申请号：US13369818
申请日：2012-02-09
申请人： Ho Wei De , Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
发明人： Ho Wei De , Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
IPC分类号： H01L21/311 , C23C16/04 , B44C1/22
CPC分类号： G03F1/38 , G03F7/70466 , H01L21/3086 , H01L21/3088 , H01L21/845 , H01L27/1211
摘要： A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer.
摘要翻译：用于图案化非矩形图案中的多个特征的方法，例如在集成电路器件上，包括提供包括具有多个细长突起的表面的基底，所述细长突起沿第一方向延伸。第一层形成在多个细长突起的表面上方和上方，并用端部切割掩模图案化。末端切割掩模包括两个几乎相邻的图案，其具有定位和配置的次分辨率特征，使得当第一层上的所得图案包括两个近似相邻的图案时，以及其间的连接。该方法还包括使用第一层上的图案切割细长突起的端部。

4. 发明申请

US20120108040A1 VAPORIZING POLYMER SPRAY DEPOSITION SYSTEM 审中-公开
标题翻译：蒸发聚合物喷雾沉积系统
公开(公告)号：US20120108040A1
公开(公告)日：2012-05-03
申请号：US12916704
申请日：2010-11-01
申请人： Ching-Yu Chang , Kuei-Liang Lu , Ming-Feng Shieh
发明人： Ching-Yu Chang , Kuei-Liang Lu , Ming-Feng Shieh
IPC分类号： H01L21/20 , B05C15/00 , B05B1/00 , B05C5/00
CPC分类号： G03F7/167 , B05D1/60
摘要： A vaporizing spray deposition device for forming a thin film includes a processing chamber, a fluid line, and a spray head coupled to the fluid line proximate the processing chamber. The fluid line is configured to transfer a polymer fluid and solvent mixture to the spray head. The spray head is configured to receive the polymer fluid and solvent mixture and to atomize the polymer fluid and solvent mixture to emit it in a substantially vaporized form to be deposited on a surface and thereby forming a thin film of the polymer on the surface after evaporation of the solvent. In an embodiment, the vaporizing spray deposition device may include a heating device to perform a hard bake process on the polymer. In an embodiment, the vaporizing spray deposition device may be configured to provide a post deposition solvent spray trim process to the thin film polymer.
摘要翻译：用于形成薄膜的蒸发喷雾沉积装置包括处理室，流体管线和连接到靠近处理室的流体管线的喷射头。流体管线被配置为将聚合物流体和溶剂混合物转移到喷雾头。喷头被配置为接收聚合物流体和溶剂混合物并且雾化聚合物流体和溶剂混合物以将其以基本蒸发的形式发射以沉积在表面上，从而在蒸发后在表面上形成聚合物的薄膜的溶剂。在一个实施方案中，蒸发喷雾沉积装置可以包括对聚合物进行硬烘烤过程的加热装置。在一个实施例中，蒸发喷雾沉积装置可以被配置为向薄膜聚合物提供后沉积溶剂喷涂装置工艺。

5. 发明授权

US08802569B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08802569B2
公开(公告)日：2014-08-12
申请号：US13418589
申请日：2012-03-13
申请人： Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
发明人： Kuei-Liang Lu , Ming-Feng Shieh , Ching-Yu Chang
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/0332 , H01L21/31058 , H01L21/31144 , H01L21/76802 , H01L21/76819 , H01L21/76837
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成多个电路器件。该方法包括在衬底上形成有机层。有机层形成在多个电路装置上。该方法包括抛光有机层以使有机层的表面平坦化。有机层在抛光之前不需要进行热处理。有机材料在抛光期间是未交联的。该方法包括在有机层的平坦化表面上沉积LT-膜。沉积在小于约150摄氏度的温度下进行。也可以不使用旋涂法进行沉积。该方法包括在LT膜上形成图案化的光致抗蚀剂层。

6. 发明授权

US09190261B2 Layer alignment in FinFET fabrication 有权
标题翻译： FinFET制造中的层对准
公开(公告)号：US09190261B2
公开(公告)日：2015-11-17
申请号：US13217702
申请日：2011-08-25
申请人： Ming-Feng Shieh , Kuei-Liang Lu
发明人： Ming-Feng Shieh , Kuei-Liang Lu
IPC分类号： H01L21/02 , H01L21/84 , H01L21/8234 , H01L21/308 , H01L23/544
CPC分类号： H01L21/02002 , H01L21/3086 , H01L21/823431 , H01L21/845 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods for aligning layers more accurately for FinFETs fabrication. An embodiment of the method, comprises: forming a plurality of dummy line features and a plurality of spacer elements according to a first pattern; removing portions of the plurality of spacer elements and portions of the plurality of dummy line features according to a second pattern; defining a reference area by removing some unwanted spacer elements according to a third pattern; aligning a front-end-of-line (FEOL) layer in X direction with the reference area defined by the third pattern; and aligning the FEOL layer in Y direction with the plurality of spacer elements defined by the first pattern. The reference area may be an active area or an alignment mask. The plurality of dummy line features and the plurality of spacer elements are formed on a substrate. The FEOL layer may be a poly layer or a shield layer.
摘要翻译： FinFET制造更准确地对准层的方法。该方法的一个实施例包括：根据第一图案形成多个假线特征和多个间隔元件; 根据第二图案去除多个间隔元件的部分和多个虚拟线特征的部分; 通过根据第三图案去除一些不需要的隔离元件来限定参考区域; 将X方向上的前端（FEOL）层与由第三图案定义的参考区对齐; 并且将Y轴方向上的FEOL层与由第一图案限定的多个间隔元件对准。参考区域可以是有源区域或对准掩模。多个虚线特征和多个间隔元件形成在基板上。 FEOL层可以是多层或屏蔽层。

7. 发明申请

US20130052793A1 Layer Alignment in FinFET Fabrication 有权
标题翻译： FinFET制造中的层对准
公开(公告)号：US20130052793A1
公开(公告)日：2013-02-28
申请号：US13217702
申请日：2011-08-25
申请人： Ming-Feng Shieh , Kuei-Liang Lu
发明人： Ming-Feng Shieh , Kuei-Liang Lu
IPC分类号： H01L21/30
CPC分类号： H01L21/02002 , H01L21/3086 , H01L21/823431 , H01L21/845 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods for aligning layers more accurately for FinFETs fabrication. An embodiment of the method, comprises: forming a plurality of dummy line features and a plurality of spacer elements according to a first pattern; removing portions of the plurality of spacer elements and portions of the plurality of dummy line features according to a second pattern; defining a reference area by removing some unwanted spacer elements according to a third pattern; aligning a front-end-of-line (FEOL) layer in X direction with the reference area defined by the third pattern; and aligning the FEOL layer in Y direction with the plurality of spacer elements defined by the first pattern. The reference area may be an active area or an alignment mask. The plurality of dummy line features and the plurality of spacer elements are formed on a substrate. The FEOL layer may be a poly layer or a shield layer.
摘要翻译： FinFET制造更准确地对准层的方法。该方法的一个实施例包括：根据第一图案形成多个假线特征和多个间隔元件; 根据第二图案去除多个间隔元件的部分和多个虚拟线特征的部分; 通过根据第三图案去除一些不需要的隔离元件来限定参考区域; 将X方向上的前端（FEOL）层与由第三图案定义的参考区对齐; 并且将Y轴方向上的FEOL层与由第一图案限定的多个间隔元件对准。参考区域可以是有源区域或对准掩模。多个虚线特征和多个间隔元件形成在基板上。 FEOL层可以是多层或屏蔽层。

8. 发明授权

US09324866B2 Structure and method for transistor with line end extension 有权
标题翻译：具有线端延伸的晶体管的结构和方法
公开(公告)号：US09324866B2
公开(公告)日：2016-04-26
申请号：US13356235
申请日：2012-01-23
申请人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
摘要翻译：本公开提供了一种半导体结构。半导体结构包括半导体衬底; 形成在半导体衬底中的隔离特征; 形成在所述半导体衬底中的第一有源区和第二有源区，其中所述第一和第二有源区在第一方向上延伸并且通过隔离特征彼此分离; 以及设置在所述隔离特征上的伪栅极，其中所述伪栅极在第一方向上从另一侧的一侧延伸到所述第一有源区域并且从另一侧向所述第二有源区域延伸。

9. 发明申请

US20130187237A1 STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION 有权
标题翻译：具有线端延伸的晶体管的结构和方法
公开(公告)号：US20130187237A1
公开(公告)日：2013-07-25
申请号：US13356235
申请日：2012-01-23
申请人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
发明人： Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/41783 , H01L29/41791 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
摘要翻译：本公开提供了一种半导体结构。半导体结构包括半导体衬底; 形成在半导体衬底中的隔离特征; 形成在所述半导体衬底中的第一有源区和第二有源区，其中所述第一和第二有源区在第一方向上延伸并且通过隔离特征彼此分离; 以及设置在所述隔离特征上的伪栅极，其中所述伪栅极在第一方向上从另一侧的一侧延伸到所述第一有源区域并且从另一侧向所述第二有源区域延伸。

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