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1. 发明授权

US06640262B1 Method and apparatus for automatically configuring a configurable integrated circuit 失效
标题翻译：用于自动配置可配置集成电路的方法和装置
公开(公告)号：US06640262B1
公开(公告)日：2003-10-28
申请号：US09467724
申请日：1999-12-20
申请人： Krishna Uppunda , Eric R. Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
发明人： Krishna Uppunda , Eric R. Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
IPC分类号： G06F15177
CPC分类号： G06F15/7867
摘要： A method and apparatus for automatically configuring a configurable integrated circuit. One embodiment comprises a method for automatically loading data including configuration data to a configurable integrated circuit upon initialization of a system in which the configurable integrated circuit is embedded. The method of one embodiment comprises storing a plurality of commands and a plurality of data elements in a non-volatile memory of the system. The method further comprises reading contents of an initial address in the non-volatile memory. If the initial address contains a command, depending upon a type of the command, the method comprises writing contents of a next address in the non-volatile memory to a register space of the configurable integrated circuit, to a configuration space of the configurable integrated circuit, or to a command space of the configurable integrated circuit.
摘要翻译：一种用于自动配置可配置集成电路的方法和装置。一个实施例包括在嵌入可配置集成电路的系统的初始化时自动将包括配置数据的数据加载到可配置集成电路的方法。一个实施例的方法包括将多个命令和多个数据元素存储在系统的非易失性存储器中。该方法还包括读取非易失性存储器中的初始地址的内容。如果初始地址包含命令，则取决于命令的类型，该方法包括将非易失性存储器中的下一个地址的内容写入可配置集成电路的寄存器空间到可配置集成电路的配置空间，或可配置集成电路的命令空间。

2. 发明授权

US06678728B1 Method and apparatus for automatically loading device status information into a network device 有权
标题翻译：将设备状态信息自动加载到网络设备中的方法和装置
公开(公告)号：US06678728B1
公开(公告)日：2004-01-13
申请号：US09454783
申请日：1999-12-03
申请人： Krishna Uppunda , Eric Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
发明人： Krishna Uppunda , Eric Davis , Nathaniel Henderson , Chi-Lie Wang , Alexander Herrera
IPC分类号： G06F15177
CPC分类号： H04L12/12 , Y02D50/40
摘要： A method and apparatus for automatically loading device status information into a network device. One embodiment comprises an apparatus in a network device, wherein the network device enters a sleep state under particular conditions. In one embodiment, the apparatus is for communicating with other devices on the network and comprises control circuitry that controls communication between the network device and the other devices on the network. The apparatus further comprises a memory device that stores configuration data for the control circuitry, wherein at least a portion of the configuration data is loaded into the control circuitry upon initialization of the network device. The apparatus further comprises a buffer that stores keep-alive data that is transmitted to a plurality of the other devices in the network to refresh the presence of the network device in the network, wherein the keep-alive data is loaded into the buffer from the memory device upon initialization of the network device.
摘要翻译：一种用于将设备状态信息自动加载到网络设备中的方法和装置。一个实施例包括网络设备中的设备，其中网络设备在特定条件下进入睡眠状态。在一个实施例中，该设备用于与网络上的其他设备进行通信，并且包括控制网络设备与网络上的其他设备之间的通信的控制电路。该装置还包括存储器件，其存储用于控制电路的配置数据，其中当网络设备初始化时，配置数据的至少一部分被加载到控制电路中。所述设备还包括缓冲器，其存储传送到网络中的多个其他设备的保持活动数据，以刷新网络中网络设备的存在，其中保持活动数据从初始化网络设备时的存储设备。

3. 发明授权

US06556580B1 Multi-function transmit packet buffer 失效
标题翻译：多功能发送包缓冲区
公开(公告)号：US06556580B1
公开(公告)日：2003-04-29
申请号：US09465984
申请日：1999-12-16
申请人： Chi-Lie Wang , Lai-Chin Lo , Ngo Thanh Ho , Krishna Uppunda
发明人： Chi-Lie Wang , Lai-Chin Lo , Ngo Thanh Ho , Krishna Uppunda
IPC分类号： H04L1256
CPC分类号： H04L49/9063 , H04L12/12 , H04L47/50 , Y02D50/40
摘要： A transmit packet buffer (TPB) is used on a network interface card (NIC) to store downloaded packets and forward them through the media access controller (MAC) and the physical layer interface (PHY) onto the wire. A multi-function TPB is implemented to allow the multiple usage of this buffer. Packets may be downloaded to this buffer through multiple sources. Different types of the packets may each be stored at predefined locations. For example, while the second half of the TPB is used to transmit keep-alive or alert-on-LAN packets, the first half may be used to compare received packets with a wake-up pattern for system wake-up. With multi-function support, various PC management functions may be implemented more effectively and with reduced cost.
摘要翻译：在网络接口卡（NIC）上使用发送分组缓冲器（TPB）来存储下载的分组，并将它们通过媒体接入控制器（MAC）和物理层接口（PHY）转发到线路上。实现多功能TPB以允许该缓冲器的多次使用。数据包可以通过多个源下载到此缓冲区。不同类型的分组可以各自存储在预定义的位置。例如，当TPB的后半部分用于传送保持活动或LAN报警时，上半部分可以用于将接收的分组与用于系统唤醒的唤醒模式进行比较。通过多功能支持，可以更有效地实现各种PC管理功能，降低成本。

4. 发明授权

US08320392B1 Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches 有权
标题翻译：用于具有动态分配的可编程缓冲器的方法和装置，以优化具有开关上的死锁避免的系统吞吐量
公开(公告)号：US08320392B1
公开(公告)日：2012-11-27
申请号：US12639554
申请日：2009-12-16
申请人： Chi-Lie Wang , Jason Z Mo
发明人： Chi-Lie Wang , Jason Z Mo
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/9005 , H04L47/6215 , H04L49/90
摘要： A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.
摘要翻译：已经公开了一种具有动态分配的可编程缓冲器的方法和装置，以优化具有在交换机上的死锁避免的系统吞吐量，其中缓冲器可用性基于用于动态分配的可编程预留大小。

5. 发明申请

US20090225769A1 Method To Support Flexible Data Transport On Serial Protocols 有权
标题翻译：在串行协议上支持灵活数据传输的方法
公开(公告)号：US20090225769A1
公开(公告)日：2009-09-10
申请号：US12043918
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90
摘要： A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).
摘要翻译：串行缓冲区通过能够以分组模式或原始数据模式运行的队列来传输分组。在分组模式下，整个分组存储在队列中。在原始数据模式下，报文头/分隔符信息不存储在队列中（仅存储数据包数据）。响应于从机读请求，可将数据包传送出队列。串行缓冲器构成响应于从读取请求的分组报头，并且从所选队列中检索指定数量的分组数据。当水位超过队列内的水位时，串行缓冲器还将数据包作为总线主机传输。串行缓冲区构建这些总线主机传输的数据包头，可以以冲洗模式或非冲洗模式（分组模式）或冲洗模式（原始数据模式）执行。

6. 发明申请

US20080205422A1 Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol 有权
标题翻译：支持系统资源访问的方法和结构实现一个轻量级协议的串行设备
公开(公告)号：US20080205422A1
公开(公告)日：2008-08-28
申请号：US11679817
申请日：2007-02-27
申请人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen
发明人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen
IPC分类号： H04L12/56
CPC分类号： H04L49/9089 , H04L47/2483 , H04L49/90 , H04L49/901
摘要： On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.
摘要翻译：使用Lite-weight协议的优先级数据包访问串行缓冲区的片上资源。在串行缓冲器上提供优先级分组路径，以支持优先级分组。正常数据包在正常的数据包路径上进行处理，该路径与优先包路径并行运行。串行缓冲区的系统资源可以根据优先级分组进行访问，而不会阻塞正常数据包的流量。因此，正常数据包可以通过串行接口支持的最大带宽流经串行缓冲器。 Lite-weight协议还支持对串行缓冲区（驻留在正常数据包路径）的队列的读访问。 Lite-weight协议还支持用于状态/错误报告的门铃命令。

7. 发明授权

US6128715A Asynchronous transmit packet buffer 失效
标题翻译：异步发送包缓冲区
公开(公告)号：US6128715A
公开(公告)日：2000-10-03
申请号：US866822
申请日：1997-05-30
申请人： Chi-Lie Wang , Ngo Thanh Ho
发明人： Chi-Lie Wang , Ngo Thanh Ho
IPC分类号： G06F5/10 , G06F5/14 , H04L12/56 , G06F12/00
CPC分类号： G06F5/14 , H04L49/90 , H04L49/901 , H04L49/9089 , G06F2205/102 , G06F2205/108
摘要： A transmit packet buffer device capable of asynchronous read and write functions is used for receiving frame data from a host and forwarding the data over a network. The device comprises dual-ported memory capable of independent write and read access, a plurality of registers for storing address pointers to locations in the memory, and a logic device coupled to the dual-ported memory and the plurality of registers for controlling downloading data into the memory at a first clock speed, and transmitting data from the memory at a second clock speed. The registers are used to store memory addresses for reference by the logic device, and the data is divided into frames.
摘要翻译：能够进行异步读写功能的发送分组缓冲器用于从主机接收帧数据并通过网络转发数据。该设备包括能够独立写入和读取访问的双端口存储器，用于存储到存储器中的位置的地址指针的多个寄存器以及耦合到双端口存储器和多个寄存器的逻辑设备，用于控制将数据下载到以第一时钟速度存储存储器，并以第二时钟速度从存储器发送数据。寄存器用于存储存储器地址供逻辑器件参考，数据被分成帧。

8. 发明授权

US08902765B1 Method and apparatus for congestion and fault management with time-to-live 有权
标题翻译：拥挤和故障管理的方法和装置与生存时间
公开(公告)号：US08902765B1
公开(公告)日：2014-12-02
申请号：US12712560
申请日：2010-02-25
申请人： Chi-Lie Wang , Jason Z Mo
发明人： Chi-Lie Wang , Jason Z Mo
IPC分类号： G01R31/08 , H04L12/841
CPC分类号： H04L47/286 , H04L47/10 , H04L47/32 , H04L49/3045 , H04L49/901
摘要： A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.
摘要翻译：已经公开了具有生存时间（TTL）的拥塞和故障管理的方法和装置。每次将数据包传输到出口端口的最终缓冲区时，相关的TTL超时计数器将加载一个值。如果在TTL超时之前数据包不能从出口端口传出，则通过从对应的虚拟输出队列（VOQ）条目中删除内存缓冲区指针来清除该数据包。

9. 发明授权

US08850089B1 Method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization 有权
标题翻译：用于统一最终缓冲区的方法和装置，具有基于指针和基于页面的流量优化方案
公开(公告)号：US08850089B1
公开(公告)日：2014-09-30
申请号：US12818767
申请日：2010-06-18
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/10 , G06F2205/106
摘要： A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.
摘要翻译：已经公开了一种用于统一的最终缓冲器的方法和装置，其具有基于指针和基于页面的用于流量优化的方案。

10. 发明授权

US08516163B2 Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface 有权
标题翻译：基于硬件的并行直接存储器访问（DMA）引擎，串行快速输入/输出SRIO接口
公开(公告)号：US08516163B2
公开(公告)日：2013-08-20
申请号：US11679820
申请日：2007-02-27
申请人： Chi-Lie Wang , Bertan Tezcan
发明人： Chi-Lie Wang , Bertan Tezcan
IPC分类号： G06F13/28 , G06F9/26
CPC分类号： G06F13/28
摘要： A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.
摘要翻译：串行缓冲器包括配置为存储从主机接收的数据包的队列。直接存储器访问（DMA）引擎从具有达到相应水印的水位的最高优先级队列接收数据分组。 DMA引擎被配置为响应于从多个DMA寄存器组中选择的DMA寄存器集合。用于配置DMA引擎的DMA寄存器组可以响应于读取的数据分组的头部中的信息，或响应于读取数据分组的队列而被选择。每个DMA寄存器集定义系统存储器中相应的缓冲区，数据包被传输到该缓冲区。每个DMA寄存器集还定义相应的缓冲器是否以卷绕模式或停止模式被访问，以及是否响应于传送到相应缓冲器中的最后地址而生成门铃信号。

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