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1. 发明授权

US08320392B1 Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches 有权
标题翻译：用于具有动态分配的可编程缓冲器的方法和装置，以优化具有开关上的死锁避免的系统吞吐量
公开(公告)号：US08320392B1
公开(公告)日：2012-11-27
申请号：US12639554
申请日：2009-12-16
申请人： Chi-Lie Wang , Jason Z Mo
发明人： Chi-Lie Wang , Jason Z Mo
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/9005 , H04L47/6215 , H04L49/90
摘要： A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.
摘要翻译：已经公开了一种具有动态分配的可编程缓冲器的方法和装置，以优化具有在交换机上的死锁避免的系统吞吐量，其中缓冲器可用性基于用于动态分配的可编程预留大小。

2. 发明申请

US20090225769A1 Method To Support Flexible Data Transport On Serial Protocols 有权
标题翻译：在串行协议上支持灵活数据传输的方法
公开(公告)号：US20090225769A1
公开(公告)日：2009-09-10
申请号：US12043918
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90
摘要： A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the selected queue. The serial buffer also transfers out packets as a bus master when a water level exceeds a water mark within a queue. The serial buffer constructs packet headers for these bus master transfers, which may be performed in a flush mode or a non-flush mode (in packet mode), or in a flush mode (in raw data mode).
摘要翻译：串行缓冲区通过能够以分组模式或原始数据模式运行的队列来传输分组。在分组模式下，整个分组存储在队列中。在原始数据模式下，报文头/分隔符信息不存储在队列中（仅存储数据包数据）。响应于从机读请求，可将数据包传送出队列。串行缓冲器构成响应于从读取请求的分组报头，并且从所选队列中检索指定数量的分组数据。当水位超过队列内的水位时，串行缓冲器还将数据包作为总线主机传输。串行缓冲区构建这些总线主机传输的数据包头，可以以冲洗模式或非冲洗模式（分组模式）或冲洗模式（原始数据模式）执行。

3. 发明申请

US20080205422A1 Method And Structure To Support System Resource Access Of A Serial Device Implementing A Lite-Weight Protocol 有权
标题翻译：支持系统资源访问的方法和结构实现一个轻量级协议的串行设备
公开(公告)号：US20080205422A1
公开(公告)日：2008-08-28
申请号：US11679817
申请日：2007-02-27
申请人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen
发明人： Chi-Lie Wang , Jason Z. Mo , Calvin Nguyen
IPC分类号： H04L12/56
CPC分类号： H04L49/9089 , H04L47/2483 , H04L49/90 , H04L49/901
摘要： On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.
摘要翻译：使用Lite-weight协议的优先级数据包访问串行缓冲区的片上资源。在串行缓冲器上提供优先级分组路径，以支持优先级分组。正常数据包在正常的数据包路径上进行处理，该路径与优先包路径并行运行。串行缓冲区的系统资源可以根据优先级分组进行访问，而不会阻塞正常数据包的流量。因此，正常数据包可以通过串行接口支持的最大带宽流经串行缓冲器。 Lite-weight协议还支持对串行缓冲区（驻留在正常数据包路径）的队列的读访问。 Lite-weight协议还支持用于状态/错误报告的门铃命令。

4. 发明授权

US08902765B1 Method and apparatus for congestion and fault management with time-to-live 有权
标题翻译：拥挤和故障管理的方法和装置与生存时间
公开(公告)号：US08902765B1
公开(公告)日：2014-12-02
申请号：US12712560
申请日：2010-02-25
申请人： Chi-Lie Wang , Jason Z Mo
发明人： Chi-Lie Wang , Jason Z Mo
IPC分类号： G01R31/08 , H04L12/841
CPC分类号： H04L47/286 , H04L47/10 , H04L47/32 , H04L49/3045 , H04L49/901
摘要： A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.
摘要翻译：已经公开了具有生存时间（TTL）的拥塞和故障管理的方法和装置。每次将数据包传输到出口端口的最终缓冲区时，相关的TTL超时计数器将加载一个值。如果在TTL超时之前数据包不能从出口端口传出，则通过从对应的虚拟输出队列（VOQ）条目中删除内存缓冲区指针来清除该数据包。

5. 发明授权

US08850089B1 Method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization 有权
标题翻译：用于统一最终缓冲区的方法和装置，具有基于指针和基于页面的流量优化方案
公开(公告)号：US08850089B1
公开(公告)日：2014-09-30
申请号：US12818767
申请日：2010-06-18
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F5/10 , G06F2205/106
摘要： A method and apparatus for unified final buffer with pointer-based and page-based scheme for traffic optimization have been disclosed.
摘要翻译：已经公开了一种用于统一的最终缓冲器的方法和装置，其具有基于指针和基于页面的用于流量优化的方案。

6. 发明授权

US08325723B1 Method and apparatus for dynamic traffic management with packet classification 有权
标题翻译：用于具有分组分类的动态流量管理的方法和装置
公开(公告)号：US08325723B1
公开(公告)日：2012-12-04
申请号：US12712516
申请日：2010-02-25
申请人： Chi-Lie Wang , Jason Z Mo
发明人： Chi-Lie Wang , Jason Z Mo
IPC分类号： H04L12/28 , G01R31/08
CPC分类号： H04L47/36 , H04L47/39 , H04L49/254
摘要： A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.
摘要翻译：已经公开了用于分组分类的动态流量管理的方法和装置，其中可以使用分组大小，变化和计数来选择信用或分组仲裁。

7. 发明授权

US07818470B2 Adaptive interrupt on serial rapid input/output (SRIO) endpoint 有权
标题翻译：串行快速输入/输出（SRIO）端点的自适应中断
公开(公告)号：US07818470B2
公开(公告)日：2010-10-19
申请号：US11863192
申请日：2007-09-27
申请人： Chi-Lie Wang , Jason Z. Mo , Bertan Tezcan
发明人： Chi-Lie Wang , Jason Z. Mo , Bertan Tezcan
IPC分类号： G06F3/00
CPC分类号： H04L47/28 , H04L47/30 , H04L47/33 , H04L49/90
摘要： A serial buffer is configured to transmit a plurality of received data packets through a data packet transfer path to a host processor. A doorbell controller of the serial buffer monitors the number of data packets transmitted to the host processor through the data packet transfer path, and estimates the number of data packets actually received by the host processor. The doorbell controller generates a doorbell command each time that the estimated number of data packets corresponds with a fixed number of data packets in a frame. The doorbell commands are transmitted to the host processor on a doorbell command path, which is faster than the data packet transfer path. The doorbell controller may estimate the number of data packets actually received by the host processor in response to a first delay value, which represents how much faster the doorbell command path is than the data packet transfer path.
摘要翻译：串行缓冲器被配置为通过数据分组传送路径将多个接收到的数据分组发送到主机处理器。串行缓冲器的门铃控制器通过数据包传送路径监视发送到主机处理器的数据包的数量，并估计主机处理器实际接收到的数据包的数量。门铃控制器每当估计的数据分组数与帧中的固定数量的数据分组对应时，就产生门铃命令。门铃命令在门铃命令路径上传送到主机处理器，该命令路径比数据包传送路径快。门铃控制器可以响应于第一延迟值来估计主机处理器实际接收的数据分组的数量，其表示门铃命令路径比数据分组传送路径多得多的速度。

8. 发明授权

US07617346B2 Rapid input/output doorbell coalescing to minimize CPU utilization and reduce system interrupt latency 有权
标题翻译：快速输入/输出门铃合并，以最大限度地减少CPU利用率并减少系统中断延迟
公开(公告)号：US07617346B2
公开(公告)日：2009-11-10
申请号：US11679823
申请日：2007-02-27
申请人： Chi-Lie Wang , Kwong Hou Mak , Jason Z. Mo
发明人： Chi-Lie Wang , Kwong Hou Mak , Jason Z. Mo
IPC分类号： G06F13/26
CPC分类号： G06F9/30094
摘要： Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.
摘要翻译：使用门铃系统实现状态/错误报告。多个标志寄存器被包括在诸如串行缓冲器的系统设备上。每个标志寄存器具有对应的地址，并存储多个标志。标志扫描控制器使用标志寄存器地址以预定的优先级顺序访问标志寄存器。在检测到标志寄存器的一个或多个标志被激活时，标志扫描控制器产生门铃命令。门铃命令包括标志寄存器地址和相应的标志。系统处理器接收门铃命令并服务激活的标志。一旦激活的标志被服务，系统处理器执行一个或多个软件写入操作来清除系统设备内的标志。系统处理器可以同时维护多个标志。系统处理器还可以同时清除多个标志。

9. 发明申请

US20090228630A1 Serial Buffer To Support Rapid I/O Logic Layer Out Of order Response With Data Retransmission 有权
标题翻译：串行缓冲器，以支持快速I / O逻辑层无序响应数据重发
公开(公告)号：US20090228630A1
公开(公告)日：2009-09-10
申请号：US12043943
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901 , H04L49/9036
摘要： Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.
摘要翻译：在串行缓冲器中，请求数据包被写入存储器缓冲器的可用存储器块，这些存储器块由空闲缓冲器指针列表标识。当请求数据包被写入存储器块时，存储块从空闲缓冲区指针列表中移除，并被添加到使用的缓冲区指针列表中。读取所使用的缓冲器指针列表中的存储器块，从而从串行缓冲器发送关联的请求包。当从存储器块读取请求数据包时，从使用的缓冲区指针列表中删除存储器块，并将其添加到请求缓冲区指针列表中。如果在超时时段内接收到相应的响应包，则将该存储器块从请求缓冲区指针列表传送到空闲缓冲区指针列表。否则，内存块从请求缓冲区指针列表传输到使用的缓冲区指针列表。

10. 发明申请

US20090225775A1 Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight Protocols 审中-公开
标题翻译：串行缓冲器支持快速I / O端点与FPGA Lite权重协议之间的可靠连接
公开(公告)号：US20090225775A1
公开(公告)日：2009-09-10
申请号：US12043934
申请日：2008-03-06
申请人： Chi-Lie Wang , Jason Z. Mo
发明人： Chi-Lie Wang , Jason Z. Mo
IPC分类号： H04J3/22
CPC分类号： H04L47/30 , H04L49/90 , H04L69/08
摘要： A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite response packets are translated into sRIO response packets compatible with the sRIO protocol. These sRIO response packets are returned to the first port, thereby providing a mechanism to acknowledge successful transmissions from the first port to the second port. Unsuccessful transmissions are identified by a timeout mechanism. The serial buffer also enables transfers from the second port to the first port in a similar manner.
摘要翻译：串行缓冲器包括被配置为实现串行快速I / O（sRIO）协议的第一端口和被配置为实现Lite-weight串行（Lite）协议）的第二端口。在第一个端口接收到的SRIO数据包被转换成与Lite协议兼容的Lite请求报文。 Lite请求数据包被传输到第二个端口。与Lite协议兼容的Lite响应报文将返回到第二个端口，以响应Lite请求报文。 Lite响应数据包被转换为与sRIO协议兼容的sRIO响应数据包。这些sRIO响应分组被返回到第一端口，从而提供一种机制来确认从第一端口到第二端口的成功传输。不成功的传输通过超时机制来识别。串行缓冲器还能够以类似的方式从第二端口传输到第一端口。

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