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1. 发明授权

US06265292B1 Method of fabrication of a novel flash integrated circuit 有权
标题翻译：一种新颖的闪存集成电路的制造方法
公开(公告)号：US06265292B1
公开(公告)日：2001-07-24
申请号：US09351498
申请日：1999-07-12
申请人： Krishna Parat , Raghupathy V. Giridhar , Cheng C. Hu , Daniel Xu , Yudong Kim , Glen Wada
发明人： Krishna Parat , Raghupathy V. Giridhar , Cheng C. Hu , Daniel Xu , Yudong Kim , Glen Wada
IPC分类号： H01L21425
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.
摘要翻译：描述了制造闪速存储器集成电路的方法。在本发明的一个实施例中，在硅衬底中形成介质填充沟槽隔离区。电介质填充沟槽隔离区域将硅衬底的第一部分与硅衬底的第二部分隔离。然后去除沟槽中的电介质的一部分，以在硅衬底的第一和第二部分之间的沟槽中露出硅衬底的一部分。然后植入离子以在硅衬底的第一部分中形成第一源极区域，并在硅衬底的第二部分中形成第二源极区域，并且在沟槽中的透明硅衬底中形成掺杂区域，其中掺杂沟槽中的区域从第一掺杂源区延伸到第二掺杂源区。

2. 发明授权

US06943071B2 Integrated memory cell and method of fabrication 有权
标题翻译：集成存储单元及其制造方法
公开(公告)号：US06943071B2
公开(公告)日：2005-09-13
申请号：US10162173
申请日：2002-06-03
申请人： Albert Fazio , Krishna Parat , Glen Wada , Neal Mielke , Rex Stone
发明人： Albert Fazio , Krishna Parat , Glen Wada , Neal Mielke , Rex Stone
IPC分类号： H01L21/285 , H01L21/336 , H01L21/60 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/11526 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L27/115 , H01L27/11536 , H01L29/66825 , H01L29/7883
摘要： A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.
摘要翻译：一种非易失性存储单元，包括形成在衬底中并限定衬底有源区的一对间隔开的浅沟槽隔离区。隧道电介质形成在衬底有源区上。浮动栅极形成在隧道电介质上，并且在间隔开的浅沟槽隔离区域之间自对准。介电层形成在浮栅上，形成在电介质层上的控制栅。源极区域和漏极区域形成在浮置栅极的相对侧上的衬底有源区域中。

3. 发明授权

US06518618B1 Integrated memory cell and method of fabrication 有权
公开(公告)号：US06518618B1
公开(公告)日：2003-02-11
申请号：US09454683
申请日：1999-12-03
申请人： Albert Fazio , Krishna Parat , Glen Wada , Neal Mielke , Rex Stone
发明人： Albert Fazio , Krishna Parat , Glen Wada , Neal Mielke , Rex Stone
IPC分类号： H01L2972
CPC分类号： H01L27/11526 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L27/115 , H01L27/11536 , H01L29/66825 , H01L29/7883
摘要： A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

4. 发明申请

US20120117306A1 SENSE OPERATION FLAGS IN A MEMORY DEVICE 有权
标题翻译：在存储器中识别操作标志
公开(公告)号：US20120117306A1
公开(公告)日：2012-05-10
申请号：US12942152
申请日：2010-11-09
申请人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
摘要： Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
摘要翻译：公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

5. 发明授权

US07835187B2 Boosting seed voltage for a memory device 有权
标题翻译：提升存储器件的种子电压
公开(公告)号：US07835187B2
公开(公告)日：2010-11-16
申请号：US12262410
申请日：2008-10-31
申请人： Satoru Tamada , Neal R Mielke , Krishna Parat
发明人： Satoru Tamada , Neal R Mielke , Krishna Parat
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/10 , G11C16/3427
摘要： A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.
摘要翻译：提供了一种使用相邻位线之间的位线位线电容来提高存储器件中的种子电压的方法和装置。该方法可以包括预充电阶段，升压阶段，均衡阶段和同相锁定。在一个实施例中，该方法可以包括两次提升种子电压。位线可以分为一个或多个段。

6. 发明申请

US20090283817A1 FLOATING GATE STRUCTURES 有权
标题翻译：浮动门结构
公开(公告)号：US20090283817A1
公开(公告)日：2009-11-19
申请号：US12165272
申请日：2008-06-30
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Srivardhan Gowda , Thomas M. Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.
摘要翻译：通常描述浮栅结构。在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率。与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

7. 发明申请

US20090001443A1 NON-VOLATILE MEMORY CELL WITH MULTI-LAYER BLOCKING DIELECTRIC 审中-公开
标题翻译：具有多层阻塞介质的非易失性存储单元
公开(公告)号：US20090001443A1
公开(公告)日：2009-01-01
申请号：US11771482
申请日：2007-06-29
申请人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
发明人： Tejas Krishnamohan , Krishna Parat , Kyu Min , Rhett T. Brewer , Thomas M. Graettinger , Nirmal Ramaswamy , M. Noel Rocklein
IPC分类号： H01L29/788
CPC分类号： H01L29/513 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234
摘要： Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.
摘要翻译：公开了一种非易失性存储单元。非易失性存储单元包括具有有源区的基板。底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。电荷存储节点设置在底部电介质层的上方。此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。在多个顶部电介质层中，设置有控制栅极。

8. 发明授权

US07183162B1 Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method 有权
标题翻译：使用牺牲柱间隔物和根据该方法形成的非易失性存储单元形成非易失性存储单元的方法
公开(公告)号：US07183162B1
公开(公告)日：2007-02-27
申请号：US11284982
申请日：2005-11-21
申请人： Steven R. Soss , Krishna Parat
发明人： Steven R. Soss , Krishna Parat
IPC分类号： H01L21/8247
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/66825 , H01L29/7881
摘要： A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the isolation bodies including respective raised isolation portions, providing the pair comprising providing a buffer layer on the substrate; providing pillar spacers on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric on the surface of the substrate after removing the buffer layer; providing a floating gate on the tunnel dielectric; reducing a height of the isolation bodies to yield corresponding isolation regions; providing source and drain regions on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.
摘要翻译：形成微电子非易失性存储单元的方法，根据该方法形成的存储单元和包括存储单元的系统。该方法包括：提供衬底; 在所述衬底上提供一对间隔开的隔离体，所述隔离体包括相应的凸起隔离部分，提供所述对，包括在所述衬底上提供缓冲层; 在凸起隔离部分的侧壁上提供柱状间隔物; 在提供柱间隔物之后去除缓冲层; 在移除缓冲层期间移除柱状间隔物; 在去除缓冲层之后在衬底的表面上提供隧道电介质; 在隧道电介质上提供浮动栅极; 降低隔离体的高度以产生相应的隔离区; 在浮动栅极的相对侧上提供源极和漏极区域; 在所述浮动栅极上提供互补电介质; 以及在所述互聚电介质上提供控制栅极以产生所述存储单元。

9. 发明申请

US20130258781A1 MEMORY DEVICES AND BIASING METHODS FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的存储器件和偏置方法
公开(公告)号：US20130258781A1
公开(公告)日：2013-10-03
申请号：US13438331
申请日：2012-04-03
申请人： Akira Goda , Yijie Zhao , Krishna Parat
发明人： Akira Goda , Yijie Zhao , Krishna Parat
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.
摘要翻译：存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位对一个或多个存储器单元串执行编程和/或擦除操作。

10. 发明授权

US08498159B2 Independent well bias management in a memory device 有权
标题翻译：存储器件中的独立阱偏置管理
公开(公告)号：US08498159B2
公开(公告)日：2013-07-30
申请号：US13465328
申请日：2012-05-07
申请人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
发明人： Akira Goda , Tomoharu Tanaka , Krishna Parat , Prashant Damle , Shafqat Ahmed
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483
摘要： Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.
摘要翻译：提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

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