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1. 发明授权

US06538653B1 Graphic processing system for displaying characters and pictures at high speed 失效
公开(公告)号：US06538653B1
公开(公告)日：2003-03-25
申请号：US08625241
申请日：1996-04-01
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G06T340
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.

2. 发明授权

US5751930A Graphic processing system 失效
标题翻译：图形处理系统
公开(公告)号：US5751930A
公开(公告)日：1998-05-12
申请号：US213820
申请日：1994-03-16
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399 , G06T3/40 , G06T3/60
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.
摘要翻译：一种用于文本显示的图形处理系统，包括由用于创建字符代码信息的存储器和处理单元组成的数据处理单元，以及由图形数据处理器和帧缓冲器组成的用于创建像素的图形数据处理单元信息。通过在数据处理单元中产生字符代码信息，从数据处理单元向图形数据处理器提供字符代码信息，通过图形数据处理器创建对应于字符代码信息的帧缓冲器上的地址来执行文本显示，使用所创建的地址从帧缓冲器的第二区域读出字符字体，将读出的字符字体写入帧缓冲器的第一区域的预定位置，并在帧的第一区域输出显示数据缓冲到显示单元。

3. 发明授权

US06697070B1 Graphic processing system 失效
标题翻译：图形处理系统
公开(公告)号：US06697070B1
公开(公告)日：2004-02-24
申请号：US09454590
申请日：1999-12-07
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G06T1100
CPC分类号： G09G5/26 , G09G5/393
摘要： A graphic processing system has a processor for managing a display area and a character font area both include within an are disposed in the address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译：图形处理系统具有用于管理显示区域的处理器和包括在地址空间内的字符字体区域。从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。图形处理系统实现了字体的高速发展。

4. 发明授权

US4947342A Graphic processing system for displaying characters and pictures at high speed 失效
标题翻译：用于高速显示字符和图片的图形处理系统
公开(公告)号：US4947342A
公开(公告)日：1990-08-07
申请号：US905173
申请日：1986-09-09
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译：图形处理系统具有用于管理包括在地址空间内的显示区域和字符字体区域的处理器。从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。图形处理系统实现了字体的高速发展。

5. 发明授权

US5610622A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US5610622A
公开(公告)日：1997-03-11
申请号：US309413
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/08
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization on with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，根据垂直扫描计数器的计数信号和CRTC的隔行控制器的输出，同步信号从同步电路得到，并被提供到其他CRTC的同步终端。用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

6. 发明授权

US4904990A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US4904990A
公开(公告)日：1990-02-27
申请号：US144279
申请日：1988-01-15
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.

7. 发明授权

US4720708A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US4720708A
公开(公告)日：1988-01-19
申请号：US686594
申请日：1984-12-26
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/00
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给其他CRTC的同步终端。用于控制其它CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

8. 发明授权

US5606338A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US5606338A
公开(公告)日：1997-02-25
申请号：US309411
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/08
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给其他CRTC的同步终端。用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

9. 发明授权

US07064756B2 Data processing apparatus and shading apparatus 失效
公开(公告)号：US07064756B2
公开(公告)日：2006-06-20
申请号：US10947275
申请日：2004-09-23
申请人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
发明人： Yasuhiro Nakatsuka , Shigeru Matsuo , Jun Satoh , Masanori Miyoshi , Koyo Katsura , Takashi Sone
IPC分类号： G06T11/00
CPC分类号： G06T1/60 , G06T11/40 , G06T15/50 , G06T15/80
摘要： In a data processor and a shading apparatus used in the data processor, the data processor selects an address based on the information of a memory or a translation look-aside buffer. Therefore, even when the same data are accessed, a different address at high speed is adopted according to the hardware, object to be processed, processing, etc. A plurality of geometric vectors are given as the parameters for the vertexes of a picture, the vectors are interpolated in the picture, and the luminance of each small area in the figure is calculated using the vectors generated by the interpolation. Therefore, a spotlight or highlight can be expressed with high accuracy and at high speed even when the amount of the hardware and the extent of the picture are small.

10. 发明授权

US06954206B2 Data processor having unified memory architecture using register to optimize memory access 失效
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器
公开(公告)号：US06954206B2
公开(公告)日：2005-10-11
申请号：US10669562
申请日：2003-09-25
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G06F13/14 , G06F13/16 , G06F13/18 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/36 , G09G5/39
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求由存储器200。当CPU总线310的访问结束时，存储器控制器400重启在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

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