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1. 发明授权

US4637124A Process for fabricating semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的工艺
公开(公告)号：US4637124A
公开(公告)日：1987-01-20
申请号：US712760
申请日：1985-03-18
申请人： Kousuke Okuyama , Norio Suzuki , Satoshi Meguro , Kouichi Nagasawa
发明人： Kousuke Okuyama , Norio Suzuki , Satoshi Meguro , Kouichi Nagasawa
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/38
CPC分类号： H01L21/823864 , H01L29/78
摘要： Herein disclosed is a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers formed simultaneously at both the sides of a gate electrode thereof. The P-channel MISFET has its source and drain regions formed by a boron ion implantation using the gate electrode and the paired side wall spacers as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode.
摘要翻译：这里公开了一种制造半导体集成电路器件的方法，该半导体集成电路器件设置有N沟道和P沟道MISFET，每个N沟道和P沟道MISFET具有在其栅电极的两侧同时形成的一对侧壁间隔物。 P沟道MISFET具有通过使用栅极电极和成对侧壁间隔物作为掩模的硼离子注入形成的源极和漏极区域。抑制具有高扩散速度的硼在栅电极下扩散。

2. 发明授权

US4549340A Method of making CMOS semiconductor device using specially positioned, retained masks, and product formed thereby 失效
标题翻译：使用专门定位的保留掩模制造CMOS半导体器件的方法，以及由此形成的产品
公开(公告)号：US4549340A
公开(公告)日：1985-10-29
申请号：US530471
申请日：1983-09-08
申请人： Kouichi Nagasawa , Shuji Ikeda , Norio Suzuki , Yoshio Sakai
发明人： Kouichi Nagasawa , Shuji Ikeda , Norio Suzuki , Yoshio Sakai
IPC分类号： H01L27/092 , H01L21/033 , H01L21/762 , H01L21/8238 , H01L27/08 , H01L27/105 , H01L29/78 , H01L21/265 , H01L21/22
CPC分类号： H01L21/033 , H01L21/76218 , H01L21/8238 , H01L27/08 , H01L27/105
摘要： Disclosed is a method of manufacturing a semiconductor device which includes MOSFETs of the two-channel conductivity types of P- and N-channel types on a single semiconductor substrate. According to the present invention, a first mask and a second mask are used. The first mask covers that surface part of the semiconductor substrate in which the P-channel type MOSFET is to be formed, and it serves as a mask when an N-type impurity is introduced into the semiconductor substrate. The first mask has a property and etching rate different from those of a film formed by the thermal oxidation of the semiconductor substrate surface. The second mask covers that surface part of the semiconductor substrate which has been formed with the N-channel type MOSFET, and it serves as a mask when a P-type impurity is introduced into the semiconductor substrate. The second mask is used as an inter-layer insulator film.
摘要翻译：公开了一种半导体器件的制造方法，该半导体器件在单个半导体衬底上包括双沟道导电类型的P沟道型和N沟道型的MOSFET。根据本发明，使用第一掩模和第二掩模。第一掩模覆盖要形成P沟道型MOSFET的半导体衬底的表面部分，并且当将N型杂质引入到半导体衬底中时，其用作掩模。第一掩模具有不同于通过半导体衬底表面的热氧化形成的膜的性质和蚀刻速率。第二掩模覆盖已经形成有N沟道型MOSFET的半导体衬底的表面部分，并且当P型杂质被引入到半导体衬底中时，其用作掩模。第二掩模用作层间绝缘膜。

3. 发明授权

US5619055A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5619055A
公开(公告)日：1997-04-08
申请号：US429882
申请日：1995-04-27
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error. The overlapping relationship for effecting the large capacitor element across the source and gate of the respective load MISFETs is provided by an ion implanting scheme of a p-type impurity into the semiconductor strip. A separate mask for ion-implantation for the formation of the source region of the load MISFET is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET之上。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由不同于导电膜的驱动MISFET组成的栅电极构成。在具有这种堆叠布置的存储器单元中，每个负载MISFET的源极区域和栅电极被图案化以具有彼此广泛重叠的关系，以形成电容器元件，使得与每个负载MISFET相关联的总体电容的增加存储单元存储节点被实现，从而减少软错误的发生。通过p型杂质离子注入到半导体条中的方式来提供跨越各个负载MISFET的源极和栅极的大电容器元件的重叠关系。添加用于形成负载MISFET的源极区域的离子注入的单独的掩模，然后以与源极区域具有广泛重叠的关系的方式添加其栅电极。

4. 发明授权

US5483083A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5483083A
公开(公告)日：1996-01-09
申请号：US028128
申请日：1993-03-09
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.
摘要翻译：提供采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFET上方。存储单元的每个负载MISFET由诸如多晶硅膜条的半导体条形成的源极，漏极和沟道区域以及由与驱动MISFET的不同层导电膜组成的栅电极组成。在用于将地电位施加到其驱动MISFET的源极区的存储单元的驱动和负载MISFET的堆叠布置中，形成作为单独导电层的布线。

5. 发明授权

US06838374B2 Semiconductor integrated circuit device and method of fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06838374B2
公开(公告)日：2005-01-04
申请号：US10170359
申请日：2002-06-14
申请人： Toshiya Uenishi , Satoshi Meguro , Masaharu Kubo , Masataka Kato , Hideo Miura , Norio Suzuki
发明人： Toshiya Uenishi , Satoshi Meguro , Masaharu Kubo , Masataka Kato , Hideo Miura , Norio Suzuki
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L21/4763
CPC分类号： H01L21/76237
摘要： To suppress oxidation of the inner walls of element isolation grooves otherwise occurring during thermal oxidation processes, a nitrogen introducing layer, that has a lower diffusion coefficient relative to an oxidizing agent, is formed at the surface portion of a silicon oxide film buried within an element isolation groove. This nitrogen introduced layer functions as a barrier layer for precluding the oxidizer (such as oxygen, water or the like) in vapor phase from diffusing into the silicon oxide film during thermal processing steps. The nitrogen introduced layer is formed by performing nitrogen ion implantation into the entire surface of a substrate and subsequently applying thermal processing to the substrate to thereby activate the nitrogen that has been doped.
摘要翻译：为了抑制在热氧化过程中发生的元件隔离槽的内壁的氧化，在埋置在元件内的氧化硅膜的表面部分形成有相对于氧化剂具有较低扩散系数的氮导入层隔离槽。该氮引入层用作阻止层，用于排除气相中的氧化剂（例如氧，水等）在热处理步骤期间扩散到氧化硅膜中。通过在衬底的整个表面中进行氮离子注入并随后对衬底进行热处理从而激活掺杂的氮而形成氮引入层。

6. 发明授权

US5700705A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5700705A
公开(公告)日：1997-12-23
申请号：US470452
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type or of n-type and p-type polycrystalline silicon films, respectively, and electrical connections are formed between the drain regions of the first and second p-channel load MISFETs with that of the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. Also, there are formed electrical connections between the polycrystalline silicon gate electrodes of the first and second load MISFETs with that of drain regions of the second and first drive MISFETs, through the poly-Si gate electrodes of the first and second drive MISFETs, in each memory cell of the SRAM, respectively, furthermore.
摘要翻译：公开了采用SRAM的一对交叉耦合CMOS反相器的类型的存储单元的制造，其中负载MISFET堆叠在半导体衬底上方和驱动MISFET上方。每个负载MISFET的制造包括在同一多晶硅膜内形成源极，漏极和沟道区域，以及由不同层导电膜（例如多晶膜）组成的栅电极，而不是驱动MISFET。具有这种堆叠布置的存储单元的制造有助于其每个负载MISFET的源极（漏极）区域和栅极电极的图案化，以使得彼此之间具有重叠关系，从而增加与每个负载MISFET相关联的有效电容存储单元存储节点。驱动和负载MISFET的栅电极分别由n型或n型和p型多晶硅膜形成，并且在第一和第二p沟道负载MISFET的漏极区之间形成电连接与第一和第二n沟道驱动MISFET的漏极区分别通过分离的多晶硅膜。此外，通过第一和第二驱动MISFET的多晶硅栅电极，在第一和第二负载MISFET的多晶硅栅电极与第二和第一驱动MISFET的漏极区域之间形成电连接此外，SRAM的存储单元分别。

7. 发明授权

US5194749A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5194749A
公开(公告)日：1993-03-16
申请号：US837689
申请日：1992-02-19
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.
摘要翻译：在CMOS型SRAM的存储单元中，具有作为源极，漏极和沟道区域的多晶硅膜的负载MISFET堆叠在驱动MISFET上，驱动MISFET和负载MISFET的栅电极由不同层中的导电膜构成。设置在多晶硅膜上的源极和漏极的面积与负载MISFET的栅电极重叠。

8. 发明授权

US5646423A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5646423A
公开(公告)日：1997-07-08
申请号：US470451
申请日：1995-06-06
申请人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
发明人： Satoshi Meguro , Kiyofumi Uchibori , Norio Suzuki , Makoto Motoyoshi , Atsuyoshi Koike , Toshiaki Yamanaka , Yoshio Sakai , Toru Kaga , Naotaka Hashimoto , Takashi Hashimoto , Shigeru Honjou , Osamu Minato
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/04 , H01L31/036
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.
摘要翻译：公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容。驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一和第二n沟道驱动MISFET分别通过单独的多晶硅膜。此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。

9. 发明授权

US4853894A Static random-access memory having multilevel conductive layer 失效
标题翻译：具有多层导电层的静态随机存取存储器
公开(公告)号：US4853894A
公开(公告)日：1989-08-01
申请号：US71749
申请日：1987-07-09
申请人： Toshiaki Yamanaka , Norio Suzuki , Yoshio Sakai , Yoshifumi Kawamoto , Osamu Minato , Koichiro Ishibashi , Nobuyuki Moriwaki , Satoshi Meguro
发明人： Toshiaki Yamanaka , Norio Suzuki , Yoshio Sakai , Yoshifumi Kawamoto , Osamu Minato , Koichiro Ishibashi , Nobuyuki Moriwaki , Satoshi Meguro
IPC分类号： H01L27/06 , H01L21/3205 , H01L21/8244 , H01L23/52 , H01L27/11
CPC分类号： H01L27/1112 , Y10S257/903
摘要： A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conductive film for fixing the sources of the driver MOS transistors to a ground voltage is formed above the principal surface of the semiconductor substrate, and this conductive film defines one electrode of a capacitance element formed on the substrate. The conductive film is formed over the load resistors formed on the semiconductor substrate so as to constitute an electric field shield for the load resistors.
摘要翻译：一种具有静电单元的半导体存储器，分别由形成在半导体衬底上的两个驱动器MOS晶体管和两个传输MOS晶体管和两个负载电阻组成，分别形成在衬底上并连接到驱动器MOS晶体管的漏极。在半导体衬底的主表面上形成用于将驱动器MOS晶体管的源极固定为接地电压的导电膜，该导电膜限定形成在衬底上的电容元件的一个电极。导电膜形成在形成在半导体衬底上的负载电阻之上，以构成用于负载电阻器的电场屏蔽。

10. 发明授权

US08850592B2 Unauthorized operation detection system and unauthorized operation detection method 有权
标题翻译：未经授权的操作检测系统和未经授权的操作检测方法
公开(公告)号：US08850592B2
公开(公告)日：2014-09-30
申请号：US12808130
申请日：2010-04-02
申请人： Makoto Kayashima , Shinichi Tsunoo , Hiroshi Nakagoe , Hiromi Isokawa , Norio Suzuki
发明人： Makoto Kayashima , Shinichi Tsunoo , Hiroshi Nakagoe , Hiromi Isokawa , Norio Suzuki
IPC分类号： G06F21/00 , G06F21/60 , G06F21/55 , G06F21/52 , H04L29/06
CPC分类号： G06F21/556 , G06F21/52 , G06F21/552 , G06F21/606 , G06F2221/0737 , G06F2221/2101 , G06F2221/2119 , H04L63/1416
摘要： The content of operations is identified and an alert is generated to an operation having a high risk of information leakage.An agent monitors, for example, operations performed with respect to a dialogue displayed on a client PC. If a file is selected by an operation performed with respect to the displayed dialogue, the agent assigns an identifier indicating a source for the file to the file. If the file is sent as an attached file, the agent identifies an output destination for the attached file as well as the source for the attached file; and if the output destination for the attached file is an external Web server and the source for the attached file is a mail server, the agent generates an alert by determining that an unauthorized operation has been executed; and then sends the generated alert to a management server.
摘要翻译：识别操作的内容，并且对具有高信息泄漏风险的操作产生警报。代理监视例如关于在客户端PC上显示的对话执行的操作。如果通过对显示的对话执行的操作来选择文件，则代理将指定文件的源的标识符分配给该文件。如果文件作为附件发送，代理将识别所附文件的输出目的地以及所附文件的源; 并且如果附加文件的输出目的地是外部Web服务器，并且所附加文件的源是邮件服务器，则代理通过确定已经执行了未经授权的操作来生成警报; 然后将生成的警报发送到管理服务器。

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