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    • 5. 发明授权
    • Semiconductor memory having two charge storage sections
    • 具有两个电荷存储部分的半导体存储器
    • US07095077B2
    • 2006-08-22
    • US10824394
    • 2004-04-15
    • Kotaro KataokaHiroshi IwataAkihide Shibata
    • Kotaro KataokaHiroshi IwataAkihide Shibata
    • H01L29/792
    • H01L29/66833H01L21/28282H01L29/7923
    • A semiconductor memory includes: a p-type semiconductor (p-type semiconductor film on a substrate, a p-type well region in a semiconductor substrate, or an insulator); a gate insulating film formed on the p-type semiconductor; a gate electrode formed on the gate insulating film; two charge storage sections formed on side walls of the gate electrode; a channel region provided below the gate electrode; and a first n-type diffusion layer region and a second n-type diffusion layer region provided to sides of the channel region, wherein: the charge storage sections are arranged to change an electric current flow between the first n-type diffusion layer region and the second n-type diffusion layer region under application of a voltage to the gate electrode according to the quantity of electric charges stored in the charge storage sections; and the first n-type diffusion layer region is set to a reference voltage, the other n-type diffusion layer region is set to a voltage greater than the reference voltage, and the gate electrode is set to a voltage greater than the reference voltage. Thus, the semiconductor memory obtained is capable of 2 bit operation and easy to miniaturize.
    • 半导体存储器包括:p型半导体(衬底上的p型半导体膜,半导体衬底中的p型阱区或绝缘体); 形成在p型半导体上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在栅电极的侧壁上的两个电荷存储部分; 设置在栅电极下方的沟道区; 以及设置在沟道区域的侧面的第一n型扩散层区域和第二n型扩散层区域,其中:电荷存储部分被布置成改变第一n型扩散层区域和 根据存储在电荷存储部中的电荷量,向栅电极施加电压的第二n型扩散层区域; 并且将第一n型扩散层区域设定为基准电压,将另一n型扩散层区域设定为大于基准电压的电压,将栅极电极设定为大于基准电压的电压。 因此,所获得的半导体存储器能够进行2位操作并且容易小型化。