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1. 发明授权

US07193319B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07193319B2
公开(公告)日：2007-03-20
申请号：US11288098
申请日：2005-11-29
申请人： Koji Sasaki , Shinji Hiramitsu , Tadaaki Kariya , Satoshi Matsuyoshi , Ryouichi Kajiwara , Shosaku Ishihara
发明人： Koji Sasaki , Shinji Hiramitsu , Tadaaki Kariya , Satoshi Matsuyoshi , Ryouichi Kajiwara , Shosaku Ishihara
IPC分类号： H01L23/34
CPC分类号： H01L23/488 , H01L23/051 , H01L23/24 , H01L24/32 , H01L24/33 , H01L2224/291 , H01L2224/29111 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/181 , H01L2924/351 , H01L2924/01026 , H01L2924/01028 , H01L2924/01083 , H01L2924/3512 , H01L2924/00 , H01L2924/00015 , H01L2924/014 , H01L2924/00012
摘要： A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10−6/° C. to 8×10−6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.
摘要翻译：提供了一种半导体器件，其中具有3×10 -6 /℃至8×10 -6 /℃的线性膨胀系数的缓冲层通过无铅焊料接合到硅芯片的上表面和下表面，该无铅焊料具有厚度不大于0.05mm，熔点不低于250℃。上缓冲层的上表面和下缓冲层的下表面分别通过无铅焊接到引线和基体上焊料厚度不小于0.15mm，熔点不低于250℃。

2. 发明申请

US20060214291A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060214291A1
公开(公告)日：2006-09-28
申请号：US11288098
申请日：2005-11-29
申请人： Koji Sasaki , Shinji Hiramitsu , Tadaaki Kariya , Satoshi Matsuyoshi , Ryouichi Kajiwara , Shosaku Ishihara
发明人： Koji Sasaki , Shinji Hiramitsu , Tadaaki Kariya , Satoshi Matsuyoshi , Ryouichi Kajiwara , Shosaku Ishihara
IPC分类号： H01L23/48
CPC分类号： H01L23/488 , H01L23/051 , H01L23/24 , H01L24/32 , H01L24/33 , H01L2224/291 , H01L2224/29111 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/181 , H01L2924/351 , H01L2924/01026 , H01L2924/01028 , H01L2924/01083 , H01L2924/3512 , H01L2924/00 , H01L2924/00015 , H01L2924/014 , H01L2924/00012
摘要： A semiconductor device is provided, in which buffer layers having a coefficient of linear expansion of 3×10−6/° C. to 8×10−6/° C. are joined to upper and lower surfaces of a silicon chip through a Pb-free solder having a thickness of not more than 0.05 mm and a melting point of not less than 250° C. The upper surface of the upper buffer layer and the lower surface of the lower buffer layer are respectively joined to a lead and a base through Pb-free solders having a thickness of not less than 0.15 mm and a melting point of not less than 250° C.
摘要翻译：提供一种半导体器件，其中具有3×10 -6 /℃至8×10 -6 /℃的线性膨胀系数的缓冲层通过无铅焊料接合到硅芯片的上表面和下表面，该无铅焊料具有厚度不大于0.05mm，熔点不低于250℃。上缓冲层的上表面和下缓冲层的下表面分别通过无铅焊接到引线和基体上焊料厚度不小于0.15mm，熔点不低于250℃。

3. 发明授权

US4728825A Bidirectional MOS linear switch 失效
标题翻译：双向MOS线性开关
公开(公告)号：US4728825A
公开(公告)日：1988-03-01
申请号：US868022
申请日：1986-05-29
申请人： Shigeru Sugayama , Tadaaki Kariya , Tatsuo Shimura , Sigeo Tomita
发明人： Shigeru Sugayama , Tadaaki Kariya , Tatsuo Shimura , Sigeo Tomita
IPC分类号： H03K17/687
CPC分类号： H03K17/6874 , H03K2217/0018
摘要： In a bidirectional linear switch in which two MOS transistors are used with their sources mutually connected, the gates and the substrates of the transistors are also respectively mutually connected and a control signal is applied to the gates. A potential of the polarity such that the substrates are reversely biased to the sources is applied between the substrates and the sources. With this constitution, the linearity of the bidirectional switch is improved.
摘要翻译：在其两个MOS晶体管与其源极相互连接的双向线性开关中，晶体管的栅极和衬底也分别相互连接，并且控制信号被施加到栅极。将基板反向偏置到源极上的极性电位施加在基板和源之间。利用这种结构，提高了双向开关的线性。

4. 发明授权

US4725770A Reference voltage circuit 失效
标题翻译：参考电压电路
公开(公告)号：US4725770A
公开(公告)日：1988-02-16
申请号：US13549
申请日：1987-02-11
申请人： Mitsuhiko Okutsu , Tatsuo Shimura , Tadaaki Kariya , Kazuyoshi Masuda
发明人： Mitsuhiko Okutsu , Tatsuo Shimura , Tadaaki Kariya , Kazuyoshi Masuda
IPC分类号： G05F3/30 , G05F3/20
CPC分类号： G05F3/30
摘要： A reference voltage circuit in which an output reference voltage is stabilized against variations in power source as well as in transistor current amplification factor h.sub.FE. In a reference voltage circuit comprising a DC power source connected to an output terminal, first and second resistors with their respective one ends commonly connected to the output terminal, a first NPN transistor with its collector shorted with its base and connected to the other end of the first resistor and its emitter grounded, a second NPN transistor with its collector connected to the other end of the second resistor and its base connected to the collector of the first NPN transistor, a third resistor connected between the emitter of the second NPN transistor and the ground, and a third NPN transistor with its collector connected to the output terminal, its base connected to the collector of the second NPN transistor and its emitter grounded, there are further provided a fourth resistor connected between the collector of the third NPN transistor and the output terminal and a PNP transistor with its base connected to the collector of the third NPN transistor, its emitter connected to the output terminal and its collector grounded.
摘要翻译：参考电压电路，其中输出参考电压针对电源的变化以及在晶体管电流放大系数hFE中稳定。在包括连接到输出端子的直流电源的参考电压电路中，第一和第二电阻器的相应的一端共同连接到输出端子，第一NPN晶体管的集电极与其基极短接并连接到另一端第一电阻器及其发射极接地，第二NPN晶体管的集电极连接到第二电阻器的另一端，其基极连接到第一NPN晶体管的集电极，第三电阻器连接在第二NPN晶体管的发射极和接地和第三NPN晶体管，其集电极连接到输出端，其基极连接到第二NPN晶体管的集电极并且其发射极接地，还提供连接在第三NPN晶体管的集电极和第三NPN晶体管的集电极之间的第四电阻器，输出端子和PNP晶体管，其基极连接到第三NPN晶体管的集电极，其发射极连接输出端子及其集电极接地。

5. 发明授权

US5148049A Circuit for driving a capacitive load utilizing thyristors 失效
标题翻译：用于驱动电容负载的电路
公开(公告)号：US5148049A
公开(公告)日：1992-09-15
申请号：US405230
申请日：1989-09-11
申请人： Mitsuhiko Okutsu , Kenji Abe , Tadaaki Kariya
发明人： Mitsuhiko Okutsu , Kenji Abe , Tadaaki Kariya
IPC分类号： G09G3/30 , G09G3/20 , H03K17/567 , H03K17/73 , H03K17/735
CPC分类号： H03K17/735 , H03K17/567 , H03K17/73
摘要： A driving circuit suitable for driving a capacitive load such as an EL display panel is disclosed, which comprises a first power source terminal; a second power source terminal; an output terminal, with which a capacitive load is connected; a source side thyristor connected between the first power source terminal and the output terminal, and supplying current to the load; a sink side thyristor connected between the second power source terminal and the output terminal and drawing-out current from the load; and a control section connected between the first power source terminal and the second power source terminal and ON-OFF controlling the source side thyristor and the sink side thyristor through a circuit arrangement coupled between the control circuit and the gates of the thyristors.

6. 发明授权

US4298881A Semiconductor device with double moat and double channel stoppers 失效
标题翻译：双沟槽和双通道塞子的半导体器件
公开(公告)号：US4298881A
公开(公告)日：1981-11-03
申请号：US138085
申请日：1980-04-07
申请人： Shuroku Sakurada , Yoichi Nakashima , Isao Kojima , Hideyuki Yagi , Tadaaki Kariya , Masayoshi Sugiyama
发明人： Shuroku Sakurada , Yoichi Nakashima , Isao Kojima , Hideyuki Yagi , Tadaaki Kariya , Masayoshi Sugiyama
IPC分类号： H01L29/73 , H01L21/331 , H01L23/31 , H01L29/06 , H01L29/74 , H01L29/744 , H01L29/747
CPC分类号： H01L29/0638 , H01L23/3178 , H01L29/0661 , H01L29/74 , H01L29/744 , H01L29/747 , H01L2924/0002
摘要： This invention concerns a so-called double-moat uni-surface type semiconductor device in which two concentric moats are provided in one main surface of the substrate and the edges of the two pn-junctions for blocking main circuit voltages applied to the device are exposed in the surfaces of the moats. Semiconductor layers having high impurity concentrations and serving as channel stoppers are formed on the semiconductor layers exposed in the one main surface of the substrate, contiguous to the moats and spaced apart from the pn-junctions, each high impurity concentration layer having the same conductivity type as the semiconductor layer on which it is formed. The moats are filled with surface passivating material.
摘要翻译：本发明涉及一种所谓的双护城河单面型半导体器件，其中两个同心的护城河设置在基板的一个主表面中，并且用于阻挡施加到该器件的主电路电压的两个pn结的边缘暴露在护城河的表面。具有高杂质浓度且用作沟道阻挡层的半导体层形成在与基片邻接并与pn结隔开的衬底的一个主表面中露出的半导体层上，每个高杂质浓度层具有相同的导电类型作为其上形成的半导体层。护城河充满表面钝化材料。

7. 发明授权

US4833587A Semiconductor switching circuit 失效
标题翻译：半导体开关电路
公开(公告)号：US4833587A
公开(公告)日：1989-05-23
申请号：US171383
申请日：1988-03-21
申请人： Shigeru Sugayama , Tadaaki Kariya , Tatsuo Shimura , Sigeo Tomita
发明人： Shigeru Sugayama , Tadaaki Kariya , Tatsuo Shimura , Sigeo Tomita
IPC分类号： H01L27/06 , H03K17/72 , H03K17/732
CPC分类号： H01L27/0641 , H03K17/72 , H03K17/732 , H01L2924/0002
摘要： A fraction of current passing through the P-emitter region and N-base region of a thyristor is by-passed to the base-emitter junction of a PNP transistor. The amount of the base current is dependent on the thyristor current. Thus, as the anode current of the thyristor increases, the base current and hence the collector current of the PNP transistor increases. The collector current by-passed to the PNP transistor is fed, via a switch which is closed during the off-time of the thyistor, to the base-collector path of an NPN transistor whose collector and emitter are respectively connected to the gate and cathode of the thyristor. The turn-on voltage across the collector and emitter of the NPN transistor accordingly becomes lower than the gate-cathode voltage of the thyristor. The base-emitter current of the NPN transistor equals the collector current of the PNP transistor, the collector current being a fraction of the anode current by-passed to the PNP transistor. A fraction of the anode current of the turned-on thyristor is utilized as the control power for driving the NPN transistor so that additional external power for turning off the thyristor becomes almost unnecessary.
摘要翻译：通过晶闸管的P发射极区域和N基极区域的电流的一部分被旁路到PNP晶体管的基极 - 发射极结。基极电流的量取决于晶闸管电流。因此，随着晶闸管的阳极电流增加，PNP晶体管的基极电流和集电极电流增加。旁路到PNP晶体管的集电极电流通过在晶体管截止时间期间闭合的开关馈送到集电极和发射极分别连接到栅极和阴极的NPN晶体管的集电极路径的晶闸管。因此，NPN晶体管的集电极和发射极两端的导通电压变得低于晶闸管的栅极 - 阴极电压。 NPN晶体管的基极 - 发射极电流等于PNP晶体管的集电极电流，集电极电流是旁路到PNP晶体管的阳极电流的一部分。导通晶闸管的阳极电流的一部分被用作用于驱动NPN晶体管的控制功率，使得几乎不需要用于关断晶闸管的附加外部电源。

8. 发明授权

US5097160A Method of transmitting pulse signal and apparatus therefor 失效
标题翻译：传输脉冲信号的方法及其设备
公开(公告)号：US5097160A
公开(公告)日：1992-03-17
申请号：US494667
申请日：1990-03-16
申请人： Shigeyuki Kawahata , Susumu Murakami , Eisuke Sato , Tadaaki Kariya , Kazunori Morozumi
发明人： Shigeyuki Kawahata , Susumu Murakami , Eisuke Sato , Tadaaki Kariya , Kazunori Morozumi
IPC分类号： H01L29/74 , H03K5/003 , H03K5/125 , H03K17/56 , H03K17/72 , H03K17/73 , H03K17/74 , H04L25/49
CPC分类号： H03K17/73 , H03K17/74 , H03K5/003
摘要： A method of transmitting a pulse signal composed of a combination of a positive pulse and a negative pulse through a semiconductor switch providing a conduction modulation in the on-state, the positive pulse and negative pulse flowing through the semiconductor switch in the forward and reverse directions, respectively, relative to the semiconductor switch. An offset current is superposed upon the pulse signal so as to make the absolute value of the positive pulse larger than that of the negative pulse.

9. 发明授权

US5083180A Lateral-type semiconductor device 失效
标题翻译：横向型半导体器件
公开(公告)号：US5083180A
公开(公告)日：1992-01-21
申请号：US595580
申请日：1990-10-11
申请人： Masato Miura , Tatsuo Shimura , Tadaaki Kariya , Norihiro Kawauchi , Sinichi Kurita
发明人： Masato Miura , Tatsuo Shimura , Tadaaki Kariya , Norihiro Kawauchi , Sinichi Kurita
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/732 , H01L29/735
CPC分类号： H01L29/735
摘要： A lateral-type semiconductor device is provided in which a p-emitter layer and a p-collector layer are formed on the exposed-surface side of an n-base layer. The exposed surfaces of the p-emitter layer and the n-base layer are substantially surrounded by the exposed surface of the p-collector layer. The n-base layer is connected to a base electrode or through a first heavily-doped region extending from under the n-base region to an exposed surface area on the outer-periphery side of the p-collector layer. In an alternative embodiment a second heavily-doped region for connecting the n-base layer and the first heavily-doped region can be provided.
摘要翻译：提供了一种横向型半导体器件，其中在n基层的暴露表面侧上形成有p发射极层和p集电极层。 p发射极层和n基层的暴露表面基本上被p集电体层的暴露表面包围。 n基层与基极电极或者从n基区域下方延伸的第一重掺杂区域连接到p集电体层的外周侧的露出表面区域。在替代实施例中，可以提供用于连接n基极层和第一重掺杂区域的第二重掺杂区域。

10. 发明授权

US4967100A Capacitive load driving apparatus 失效
标题翻译：电容式负载驱动装置
公开(公告)号：US4967100A
公开(公告)日：1990-10-30
申请号：US286861
申请日：1988-12-20
申请人： Mitsuhiko Okutsu , Tadaaki Kariya , Kouji Kawamoto , Syuzoh Kaneko , Yasuhiro Mashiko
发明人： Mitsuhiko Okutsu , Tadaaki Kariya , Kouji Kawamoto , Syuzoh Kaneko , Yasuhiro Mashiko
IPC分类号： G09G3/22 , G09G3/30 , H03K17/567 , H03K17/62 , H03K17/66
CPC分类号： H03K17/667 , H03K17/567 , H03K17/6285
摘要： A capacitive load driving apparatus which has a plurality of first switching elements connected between a plurality of parallel loads and a first power source terminal for switching currents which charge the loads. There is furthermore provided a plurality of bipolar transistors connected between connecting points (of the first switching elements and the loads) and a second power source terminal for discharging charges stored in the loads and a plurality of second switching elements connected between a third power source terminal and bases of the bipolar transistor, respectively, for switching base currents supplied from the third power source terminal to the bipolar transistors. In addition, the capacitive load driving apparatus has a logic circuit connected to an input terminal for providing driving signals which turn off selectively one or all of the second switching elements in accordance with a signal from the input terminal, and it has a resistor connected between the third power source terminal and the second switching elements.
摘要翻译：一种容性负载驱动装置，其具有连接在多个并联负载之间的多个第一开关元件和用于切换对负载充电的电流的第一电源端子。此外还提供了连接在第一开关元件和负载的连接点之间的多个双极晶体管和用于放电存储在负载中的电荷的第二电源端子以及连接在第三电源端子之间的多个第二开关元件和双极晶体管的基极，用于将从第三电源端子提供的基极电流切换到双极晶体管。此外，电容性负载驱动装置具有连接到输入端子的逻辑电路，用于提供根据来自输入端子的信号选择性地关闭第二开关元件中的一个或全部的驱动信号，并且其具有连接在第三电源端子和第二开关元件。

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