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    • 4. 发明授权
    • Surface-mount flat package semiconductor device
    • 表面贴装扁平封装半导体器件
    • US5521429A
    • 1996-05-28
    • US344424
    • 1994-11-23
    • Tsutomu AonoTakayoshi Nishi
    • Tsutomu AonoTakayoshi Nishi
    • H01L23/495H01L23/28H01L23/36
    • H01L23/49562H01L23/49548H01L2224/48091H01L2224/48247H01L24/48H01L2924/00014H01L2924/09701H01L2924/14H01L2924/181
    • A surface mount flat package for a semiconductor device includes a number of leads on a lead frame. At least one of the leads is straight with a thick section and a thin section. Part of the thin section is inside a protective medium and part extends outside. A bottom surface of the part extending outside the protective medium serves as a connection terminal for the semiconductor device. Another lead is an island lead that has a bonding island on an upper surface thereof. The island lead has a thick section and a thin section. The bonding island is on the thin section. The thin section is entirely within the protective medium. A bottom surface of the thick section is exposed outside the protective medium to serve as a connection terminal. The bottom surfaces of the thick sections are coplanar with each other and preferably coplanar with a bottom surface of the package.
    • 用于半导体器件的表面贴装扁平封装包括引线框架上的多个引线。 引线中的至少一个是直的,具有厚的部分和薄的部分。 部分薄壁部分在保护介质的内部,部分延伸到外面。 延伸到保护介质外部的部分的底表面用作半导体器件的连接端子。 另一引线是在其上表面具有接合岛的岛引线。 岛上有一个厚实的部分和薄的部分。 接合岛在薄的部分。 薄部分完全在保护介质内。 厚壁的底面暴露在保护介质的外面,作为连接端子。 厚部分的底表面彼此共面并且优选地与包装的底表面共面。