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1. 发明申请

US20070052717A1 3D GRAPHICS PROCESSING METHOD AND DEVICE 审中-公开
标题翻译： 3D图形处理方法和设备
公开(公告)号：US20070052717A1
公开(公告)日：2007-03-08
申请号：US11425643
申请日：2006-06-21
申请人： Ko-Fang Wang , Hung-Chang Chen , Yu-Chang Wang
发明人： Ko-Fang Wang , Hung-Chang Chen , Yu-Chang Wang
IPC分类号： G09G5/00
CPC分类号： G06T11/40 , G06T15/005
摘要： A X-Y plane is divided into a plurality of tile rows. Each tile row covered by a triangle to be processed includes one or more tiles. The tiles in the same tile row are rastered in a specified order.
摘要翻译： X-Y平面被分成多个瓦片行。由待处理的三角形覆盖的每个瓦片行包括一个或多个瓦片。同一瓦片行中的瓦片按照指定的顺序进行扫描。

2. 发明授权

US06715061B1 Multimedia-instruction acceleration device for increasing efficiency and method for the same 有权
标题翻译：多媒体指令加速装置提高效率和方法相同
公开(公告)号：US06715061B1
公开(公告)日：2004-03-30
申请号：US09614542
申请日：2000-07-12
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F9302
CPC分类号： G06F9/3001 , G06F9/30025 , G06F9/30145 , G06F9/3877 , Y10S707/99945 , Y10S707/99948
摘要： The present invention proposes a multimedia-instruction acceleration device for increasing efficiency and a method for the same, which uses instruction strings having a floating-point value check field to execute commands of single-instruction/multi-data format, and further transforms the floating-point value to a fixed one. The present invention can effectively save executing time and simplify numerical calculation process, and can fully exploit memory space to achieve the object of increasing acceleration operation and execution of multimedia instructions.
摘要翻译：本发明提出一种用于提高效率的多媒体指令加速装置及其方法，其使用具有浮点值检查字段的指令串来执行单指令/多数据格式的命令，并进一步转换浮动将值设置为固定值。本发明可以有效地节省执行时间并简化数值计算过程，可以充分利用存储空间来实现增加加速操作和执行多媒体指令的目标。

3. 发明授权

US08423600B2 Accumulating operator and accumulating method for floating point operation 有权
标题翻译：积分运算符和浮点运算的累积方法
公开(公告)号：US08423600B2
公开(公告)日：2013-04-16
申请号：US11032486
申请日：2005-01-10
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483
摘要： An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The accumulating operator comprises a splitter dividing the first floating point number into a third floating point number and a compensation number, wherein an exponent of the third floating point number is equal to or greater than the exponent of the second floating point number; an accumulator electrically connected to the splitter for operating the second and third floating point numbers to realize a fourth floating point number; and a compensator electrically connected to the splitter and the accumulator for operating the fourth floating point number and the compensation number to realize the output floating point number. Via compensation, the precision of the floating point operation can be improved.
摘要翻译：累积运算符适用于数字数据处理器，以响应于第一浮点数和第二浮点数实现输出浮点数。累积运算符包括将第一浮点数分成第三浮点数和补偿数的分割器，其中第三浮点数的指数等于或大于第二浮点数的指数; 蓄电池，电连接到所述分路器，用于操作所述第二和第三浮点数以实现第四浮点数; 以及补偿器，电连接到分路器和累加器，用于操作第四浮点数和补偿数，以实现输出浮点数。通过补偿，可以提高浮点运算的精度。

4. 发明授权

US09262631B2 Embedded device and control method thereof 有权
标题翻译：嵌入式设备及其控制方法
公开(公告)号：US09262631B2
公开(公告)日：2016-02-16
申请号：US13677479
申请日：2012-11-15
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F9/00 , G06F21/55 , G06F9/44 , H04L9/32
CPC分类号： G06F21/554 , G06F9/4401 , H04L9/3247
摘要： An embedded device including a random access memory (RAM) and a processor is provided. The processor includes a processor core and an authentication module. The RAM stores data-to-be-authenticated. The data includes a program code to be executed by the processor core. The authentication module periodically accesses and authenticates the data-to-be-authenticated in the RAM. When the authentication module deems that the program code in the RAM loses its integrity, the authentication module interrupts the processor from further executing the program code.
摘要翻译：提供了包括随机存取存储器（RAM）和处理器的嵌入式装置。处理器包括处理器核心和认证模块。 RAM存储待认证的数据。数据包括要由处理器核心执行的程序代码。认证模块周期性地访问和认证在RAM中被认证的数据。当认证模块认为RAM中的程序代码失去其完整性时，认证模块会中断处理器进一步执行程序代码。

5. 发明申请

US20080086653A1 POWER MANAGEMENT METHODS AND SYSTEMS 有权
标题翻译：电力管理方法与系统
公开(公告)号：US20080086653A1
公开(公告)日：2008-04-10
申请号：US11758691
申请日：2007-06-06
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/329 , Y02D10/24
摘要： Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.
摘要翻译：电源管理方法和系统。首先，记录处理数据单元的处理单元的运行周期。根据运行周期和性能要求生成门控信号，并根据门控信号调整工作时钟。此后，将调整后的工作信号提供给处理单元。

6. 发明申请

US20050177610A1 Accumulating operator and accumulating method for floating point operation 有权
标题翻译：积分运算符和浮点运算的累积方法
公开(公告)号：US20050177610A1
公开(公告)日：2005-08-11
申请号：US11032486
申请日：2005-01-10
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F7/42 , G06F7/50 , G06F7/544
CPC分类号： G06F7/5443 , G06F7/483
摘要： An accumulating operator is applicable to a digital data processor to realize an output floating point number in response to a first floating point number and a second floating point number. The accumulating operator comprises a splitter dividing the first floating point number into a third floating point number and a compensation number, wherein an exponent of the third floating point number is equal to or greater than the exponent of the second floating point number; an accumulator electrically connected to the splitter for operating the second and third floating point numbers to realize a fourth floating point number; and a compensator electrically connected to the splitter and the accumulator for operating the fourth floating point number and the compensation number to realize the output floating point number. Via compensation, the precision of the floating point operation can be improved.
摘要翻译：累积运算符适用于数字数据处理器，以响应于第一浮点数和第二浮点数实现输出浮点数。累积运算符包括将第一浮点数分成第三浮点数和补偿数的分割器，其中第三浮点数的指数等于或大于第二浮点数的指数; 蓄电池，电连接到所述分路器，用于操作所述第二和第三浮点数以实现第四浮点数; 以及补偿器，电连接到分路器和累加器，用于操作第四浮点数和补偿数，以实现输出浮点数。通过补偿，可以提高浮点运算的精度。

7. 发明授权

US07793133B2 Power management method and system based on data unit running cycle and performance requirement 有权
标题翻译：基于数据单元运行周期和性能要求的电源管理方法和系统
公开(公告)号：US07793133B2
公开(公告)日：2010-09-07
申请号：US11758691
申请日：2007-06-06
申请人： Ko-Fang Wang
发明人： Ko-Fang Wang
IPC分类号： G06F1/00 , G06F1/26 , G06F15/00 , G06F17/00 , G06F15/16 , H04L12/28 , H04J3/16 , H04J3/06 , H03K17/00
CPC分类号： G06F1/3203 , G06F1/329 , Y02D10/24
摘要： Power management methods and systems. First, a running cycle of a processing unit processing a data unit is recorded. A gating signal is generated according to the running cycle and a performance requirement, and a working clock is adjusted according to the gating signal. Thereafter, the adjusted working signal is provided to the processing unit.
摘要翻译：电源管理方法和系统。首先，记录处理数据单元的处理单元的运行周期。根据运行周期和性能要求生成门控信号，并根据门控信号调整工作时钟。此后，将调整后的工作信号提供给处理单元。

8. 发明申请

US20080198166A1 MULTI-THREADS VERTEX SHADER, GRAPHICS PROCESSING UNIT, AND FLOW CONTROL METHOD 审中-公开
标题翻译：多线程VERTEX SHADER，图形处理单元和流量控制方法
公开(公告)号：US20080198166A1
公开(公告)日：2008-08-21
申请号：US11675700
申请日：2007-02-16
申请人： Hsine-Chu Chung , Chit-Keng Huang , Ko-Fang Wang
发明人： Hsine-Chu Chung , Chit-Keng Huang , Ko-Fang Wang
IPC分类号： G06T1/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.
摘要翻译：顶点着色器顶点着色器包括指令寄存器文件，流控制器，线程仲裁器和算术逻辑单元（ALU）管道。指令寄存器文件存储多个指令。同时执行多个线程的流量控制器从线程的指令寄存器文件中读取指令，并访问线程的顶点数据。线程仲裁器检查线程中指令的依赖性，并根据依赖性检查的结果和线程执行优先级来选择要执行的线程。算术逻辑单元（ALU）管接收用于执行由线程仲裁器为三维（3D）图形计算选择的线程的指令的顶点数据。

9. 发明申请

US20080122843A1 MULTI-THREAD VERTEX SHADER, GRAPHICS PROCESSING UNIT AND FLOW CONTROL METHOD 审中-公开
标题翻译：多线程VERTEX SHADER，图形处理单元和流量控制方法
公开(公告)号：US20080122843A1
公开(公告)日：2008-05-29
申请号：US11458706
申请日：2006-07-20
申请人： Hsine-Chu Chung , Ko-Fang Wang , Chit-Keng Huang
发明人： Hsine-Chu Chung , Ko-Fang Wang , Chit-Keng Huang
IPC分类号： G06T15/50 , G06F9/312 , G06T15/00
CPC分类号： G06T15/005 , G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/3838 , G06F9/3851 , G06T15/80
摘要： A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block. The flow controller is configured to perform retrieving the flow control instructions in order from the flow control instruction register file, determining at least one macro block of the macro instruction register file to be executed in accordance with the retrieved flow control instruction and the dependency information thereof, selecting one of the plurality of threads for executing the determined macro block in a predetermined thread schedule policy, and accessing vertex data for the threads.
摘要翻译：提供了一个用于在顶点数据上的多个线程中执行操作的逻辑单元。逻辑单元包括宏指令寄存器文件，流控制指令寄存器文件和流控制器。宏指令寄存器文件存储宏块，每个宏块包括至少一个指令。流控制指令寄存器文件存储流控制指令，每个流控制指令包括至少一个被叫宏块的被叫宏块和依赖信息。流控制器被配置为根据流程控制指令寄存器文件依次检索流控制指令，根据检索到的流控制指令及其依赖信息确定要执行的宏指令寄存器文件的至少一个宏块选择所述多个线程中的一个用于在预定的线程调度策略中执行所确定的宏块，以及访问所述线程的顶点数据。

10. 发明申请

US20080024510A1 TEXTURE ENGINE, GRAPHICS PROCESSING UNIT AND VIDEO PROCESSING METHOD THEREOF 审中-公开
标题翻译：纹理发动机，图形处理单元及其视频处理方法
公开(公告)号：US20080024510A1
公开(公告)日：2008-01-31
申请号：US11460319
申请日：2006-07-27
申请人： Chuan-Chen Lee , Ming-Hsuan Tan , Ko-Fang Wang
发明人： Chuan-Chen Lee , Ming-Hsuan Tan , Ko-Fang Wang
IPC分类号： G09G5/00
CPC分类号： G06T15/04 , G06T2200/28
摘要： The texture engine, provided in this disclosure, comprises a texel location calculator, a texture cache unit, and a video processing unit. The texel location calculator receives a texture and video request for a pixel, including location information of texture data for the pixel in a texture map stored in a memory unit and information of video processing required for the pixel. The texel location calculator computes memory addresses of the texture data in the memory unit and graphics data required for the pixel when performing the video processing specified in the texture and video request in the memory unit. The texture cache unit retrieves a copy of the graphics data and texture data from the memory unit with the memory addresses computed by the texel location calculator. The video processing unit receives the graphics data to perform the video processing specified in the texture and video request on the graphics data.
摘要翻译：在本公开中提供的纹理引擎包括纹理位置计算器，纹理高速缓存单元和视频处理单元。纹素位置计算器接收对像素的纹理和视频请求，包括存储在存储器单元中的纹理映射中的像素的纹理数据的位置信息和像素所需的视频处理的信息。纹理位置计算器在执行存储器单元中的纹理和视频请求中指定的视频处理时，计算存储器单元中的纹理数据的存储器地址和像素所需的图形数据。纹理缓存单元利用由纹素位置计算器计算的存储器地址从存储器单元检索图形数据和纹理数据的副本。视频处理单元接收图形数据以执行纹理和视频请求中对图形数据指定的视频处理。

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