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1. 发明授权

US08247281B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers 有权
标题翻译：通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术
公开(公告)号：US08247281B2
公开(公告)日：2012-08-21
申请号：US12822789
申请日：2010-06-24
申请人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
发明人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译：在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

2. 发明授权

US08357575B2 Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers 有权
标题翻译：通过改变应力介电覆盖层的去除速率，在替代浇口方法中暴露占位符材料的技术
公开(公告)号：US08357575B2
公开(公告)日：2013-01-22
申请号：US13550435
申请日：2012-07-16
申请人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
发明人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译：在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

3. 发明申请

US20100330790A1 TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS 有权
标题翻译：通过修改压电介质覆盖层的去除速率来更换替代门方法中的位置材料的技术
公开(公告)号：US20100330790A1
公开(公告)日：2010-12-30
申请号：US12822789
申请日：2010-06-24
申请人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
发明人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译：在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

4. 发明申请

US20120282764A1 TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS 有权
标题翻译：通过修改压电介质覆盖层的去除速率来更换替代门方法中的位置材料的技术
公开(公告)号：US20120282764A1
公开(公告)日：2012-11-08
申请号：US13550435
申请日：2012-07-16
申请人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
发明人： Klaus Hempel , Patrick Press , Vivien Schroeder , Berthold Reimer , Johannes Groschopf
IPC分类号： H01L21/283 , H01L21/302
CPC分类号： H01L21/823425 , H01L21/31055 , H01L21/31111 , H01L21/76825 , H01L21/76829 , H01L21/7684 , H01L21/823412 , H01L21/823807 , H01L29/7843
摘要： In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.
摘要翻译：在替代栅极方法中，通过例如在湿化学蚀刻步骤或CMP工艺期间，基于增强的工艺均匀性来暴露牺牲栅极材料，通过通过离子注入在层间绝缘材料中形成改性部分。因此，当应用CMP工艺时，在施加蚀刻工艺或避免过度抛光时间的同时，可以以更高的去除速率去除损坏的部分，同时避免产生聚合物污染物。

5. 发明授权

US08679924B2 Self-aligned multiple gate transistor formed on a bulk substrate 有权
标题翻译：形成在本体衬底上的自对准多栅极晶体管
公开(公告)号：US08679924B2
公开(公告)日：2014-03-25
申请号：US13017558
申请日：2011-01-31
申请人： Andy Wei , Vivien Schroeder , Thilo Scheiper , Thomas Werner , Johannes Groschopf
发明人： Andy Wei , Vivien Schroeder , Thilo Scheiper , Thomas Werner , Johannes Groschopf
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.
摘要翻译：可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

6. 发明申请

US20110291196A1 Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate 有权
标题翻译：在大量衬底上形成的自对准多栅晶体管
公开(公告)号：US20110291196A1
公开(公告)日：2011-12-01
申请号：US13017558
申请日：2011-01-31
申请人： Andy Wei , Vivien Schroeder , Thilo Scheiper , Thomas Werner , Johannes Groschopf
发明人： Andy Wei , Vivien Schroeder , Thilo Scheiper , Thomas Werner , Johannes Groschopf
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Three-dimensional transistors in a bulk configuration may be formed on the basis of gate openings or gate trenches provided in a mask material. Hence, self-aligned semiconductor fins may be efficiently patterned in the underlying active region in a portion defined by the gate opening, while other gate openings may be efficiently masked, in which planar transistors are to be provided. After patterning the semiconductor fins and adjusting the effective height thereof, the further processing may be continued on the basis of process techniques that may be commonly applied to the planar transistors and the three-dimensional transistors.
摘要翻译：可以基于设置在掩模材料中的栅极开口或栅极沟槽形成体构造的三维晶体管。因此，可以在由栅极开口限定的部分中的底层有源区域中有效地图案化自对准半导体鳍片，同时可以有效地屏蔽其中的栅极开口，其中将提供平面晶体管。在图案化半导体鳍片并调整其有效高度之后，可以基于通常应用于平面晶体管和三维晶体管的工艺技术来继续进一步的处理。

7. 发明授权

US08021942B2 Method of forming CMOS device having gate insulation layers of different type and thickness 有权
标题翻译：形成具有不同类型和厚度的栅极绝缘层的CMOS器件的方法
公开(公告)号：US08021942B2
公开(公告)日：2011-09-20
申请号：US12049548
申请日：2008-03-17
申请人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
发明人： Andy Wei , Andrew Waite , Martin Trentzsch , Johannes Groschopf , Gunter Grasshoff , Andreas Ott
IPC分类号： H01L21/8238 , H01L21/70 , H01L27/092
CPC分类号： H01L21/82345 , H01L21/823462 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/088 , H01L27/0922 , H01L29/66545 , H01L29/7843 , H01L29/7848 , Y10S438/926
摘要： In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
摘要翻译：在通过高k金属栅极结构代替常规栅电极结构的工艺顺序中，例如通过使用高选择性蚀刻步骤，附加掩模步骤的数量可以保持在低水平，从而保持与常规栅极结构的高度兼容性 CMOS技术。此外，本文公开的技术使得能够与前端处理技术和后端处理技术兼容，从而允许将已建立的应变诱发机制集成在晶体管级以及接触级中。

8. 发明申请

US20110269381A1 Planarization of a Material System in a Semiconductor Device by Using a Non-Selective In Situ Prepared Slurry 有权
标题翻译：通过使用非选择性原位制备的浆料对半导体器件中的材料系统进行平面化
公开(公告)号：US20110269381A1
公开(公告)日：2011-11-03
申请号：US12969969
申请日：2010-12-16
申请人： Johannes Groschopf , Rico Hueselitz , Marco Kitsche , Katja Steffen
发明人： Johannes Groschopf , Rico Hueselitz , Marco Kitsche , Katja Steffen
IPC分类号： B24B1/00
CPC分类号： H01L21/31053 , H01L29/66545 , H01L29/7833
摘要： For complex CMP processes requiring the removal of different dielectric materials, possibly in the presence of a polysilicon material, a slurry material may be adapted at the point of use by selecting an appropriate pH value and avoiding agglomeration of the abrasive particles. The in situ preparation of the slurry material may also enable a highly dynamic adaptation of the removal conditions, for instance when exposing the polysilicon material of gate electrode structures in replacement gate approaches.
摘要翻译：对于需要去除不同介电材料（可能存在多晶硅材料）的复杂CMP工艺，可以通过选择适当的pH值并避免磨料颗粒的团聚，在使用时适应浆料。泥浆材料的原位制备还可以实现去除条件的高度动态适应，例如当在替代浇口方法中暴露栅电极结构的多晶硅材料时。

9. 发明授权

US07767508B2 Method for forming offset spacers for semiconductor device arrangements 有权
标题翻译：用于形成用于半导体器件布置的偏置间隔物的方法
公开(公告)号：US07767508B2
公开(公告)日：2010-08-03
申请号：US11580952
申请日：2006-10-16
申请人： Philip A. Fisher , Laura A. Brown , Johannes Groschopf , Huicai Zhong
发明人： Philip A. Fisher , Laura A. Brown , Johannes Groschopf , Huicai Zhong
IPC分类号： H01L21/338
CPC分类号： H01L29/4983 , H01L21/31144 , H01L29/66659 , H01L29/66772
摘要： Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.
摘要翻译：提供了用于制造用于改善晶体管短沟道控制的突发和可调偏移间隔物的方法。这些方法包括在电介质层内形成栅电极，仅露出栅电极的顶部。例如，通过选择性外延生长将硅添加到栅电极的顶部。介电层的蚀刻是在栅电极的顶部添加硅作为硅掩模进行的，以防止直接在硅掩模下面的电介质层的蚀刻，该掩模包括在栅电极侧壁上的突出端。蚀刻以生产价值的方式产生偏移间隔物，并且可以用于形成不对称宽度的偏移间隔物。通过在微加载方案中运行该方法，可以在较窄的多晶硅栅极特征上产生更宽的偏移间隔物，从而改善Vt滚降。

10. 发明申请

US20070049184A1 RETAINING RING STRUCTURE FOR ENHANCED REMOVAL RATE DURING FIXED ABRASIVE CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译：固定磨料化学机械抛光期间增强移除速度的保持环结构
公开(公告)号：US20070049184A1
公开(公告)日：2007-03-01
申请号：US11161963
申请日：2005-08-24
申请人： Rajasekhar Venigalla , Timothy McCormack , Johannes Groschopf
发明人： Rajasekhar Venigalla , Timothy McCormack , Johannes Groschopf
IPC分类号： B24B29/00
CPC分类号： B24B37/32
摘要： A retaining ring structure for a chemical mechanical polishing (CMP) apparatus includes a plurality of protrusions formed on a bottom surface of a retaining ring configured for retaining a workpiece to be polished, the protrusions disposed so as to be in contact with a polishing pad during a polishing operation on the workpiece.
摘要翻译：用于化学机械抛光（CMP）装置的保持环结构包括形成在保持环的底表面上的多个突起，所述保持环被构造成用于保持待抛光的工件，所述突起设置成与抛光垫接触，对工件进行抛光操作。

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