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1. 发明申请

US20050146355A1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US20050146355A1
公开(公告)日：2005-07-07
申请号：US10747748
申请日：2003-12-29
申请人： Kiyoshi Kase , May Len , Dzung Tran
发明人： Kiyoshi Kase , May Len , Dzung Tran
IPC分类号： H03K3/356 , H03K17/10 , H03K19/094
CPC分类号： H03K17/102 , H03K3/356008 , H03K3/356113
摘要： A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.
摘要翻译：具有不同阈值电压的交叉耦合反相器的电平移位器。在上电期间，电平转换器的输出被拉到已知的电压状态。在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

2. 发明申请

US20070194804A1 Electronic device and method 有权
标题翻译：电子设备和方法
公开(公告)号：US20070194804A1
公开(公告)日：2007-08-23
申请号：US11360724
申请日：2006-02-23
申请人： Kiyoshi Kase , Dzung Tran
发明人： Kiyoshi Kase , Dzung Tran
IPC分类号： H03K19/003 , H03K17/16
CPC分类号： H03K19/01721
摘要： A current boost module receives a signal from the input and the output of a buffer to determine whether the buffer is transitioning between logic states. When the buffer is transitioning, a boost current is provided to a load connected to the buffer output to supplement the current from buffer output, thereby facilitating transition of a signal at the load. The current boost module can shut down the boost current before the signal at the load completes its transition from one logic state to the other.
摘要翻译：当前升压模块接收来自缓冲器的输入和输出的信号，以确定缓冲器是否在逻辑状态之间转换。当缓冲器正在转换时，向连接到缓冲器输出的负载提供升压电流，以补充来自缓冲器输出的电流，从而便于负载处的信号转换。当前的升压模块可以在负载处的信号完成其从一个逻辑状态转换到另一个逻辑状态之前关闭升压电流。

3. 发明授权

US07667492B2 Input buffer 有权
标题翻译：输入缓冲区
公开(公告)号：US07667492B2
公开(公告)日：2010-02-23
申请号：US12004617
申请日：2007-12-21
申请人： Kiyoshi Kase , May Len , Dzung T. Tran
发明人： Kiyoshi Kase , May Len , Dzung T. Tran
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.
摘要翻译：用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。响应于输入信号上升到较低阈值以上而输出第二逻辑值。此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

4. 发明申请

US20070183549A1 Adaptive variable length pulse synchronizer 有权
标题翻译：自适应可变长度脉冲同步器
公开(公告)号：US20070183549A1
公开(公告)日：2007-08-09
申请号：US11349874
申请日：2006-02-08
申请人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
发明人： John Angello , Satyavathi Akella , Kiyoshi Kase , May Len
IPC分类号： H04L25/38
CPC分类号： H04L25/38 , H04L7/0008
摘要： An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.
摘要翻译：一种自适应可变长度脉冲同步器，包括状态保持器电路，异步脉冲沿检测电路，数据同步电路和脉冲沿同步电路。状态保持电路检测异步脉冲的前沿。在状态保持电路检测到前沿之后，异步脉冲沿检测电路检测异步脉冲的后沿。在检测到异步脉冲之后，异步脉冲沿检测电路还提供与时钟信号同步的脉冲。数据同步电路锁存异步数据，并响应于同步脉冲提供同步数据。在提供同步数据之后，脉冲沿同步提供同步就绪信号。在一个实施例中，同步脉冲发生在时钟的连续上升沿之间，而响应于时钟的中间下降沿提供同步就绪信号。

5. 发明申请

US20060012356A1 Voltage regulator with adaptive frequency compensation 有权
标题翻译：具有自适应频率补偿的稳压器
公开(公告)号：US20060012356A1
公开(公告)日：2006-01-19
申请号：US10891811
申请日：2004-07-15
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.
摘要翻译：电压调节器包括第一和第二放大器级，输出级和可变零电路。第一放大器级耦合以接收参考电压并引入电压调节器的第一极。第二放大器级耦合到第一放大器级并引入电压调节器的第二极。输出级耦合到第二放大器级，具有输出驱动器，并且被耦合以提供基于参考电压的输出电压。可变零电路耦合到第一放大器级，第二放大级和输出级。基于输出驱动器的栅极 - 源极电压和输出驱动器的漏极 - 源极电压，可变零电路提供零以补偿电压调节器的第一极点或第二极点中的至少一个极点。

6. 发明授权

US07479813B2 Low voltage circuit with variable substrate bias 有权
标题翻译：具有可变衬底偏置的低压电路
公开(公告)号：US07479813B2
公开(公告)日：2009-01-20
申请号：US11424132
申请日：2006-06-14
申请人： Kiyoshi Kase , Dzung T. Tran , May Len
发明人： Kiyoshi Kase , Dzung T. Tran , May Len
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G05F3/205
摘要： In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.
摘要翻译：在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。该电路用驱动级修改输入信号以提供补码形式的输出信号。电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。偏置晶体管具有耦合到输入信号端子的控制电极。输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。电路输出阻抗的线性提高，RF干扰降低。还提供较低的电压操作。

7. 发明申请

US20080122520A1 LOW VOLTAGE CIRCUIT WITH VARIABLE SUBSTRATE BIAS 有权
标题翻译：具有可变基板偏置的低电压电路
公开(公告)号：US20080122520A1
公开(公告)日：2008-05-29
申请号：US11424132
申请日：2006-06-14
申请人： Kiyoshi Kase , Dzung T. Tran , May Len
发明人： Kiyoshi Kase , Dzung T. Tran , May Len
IPC分类号： G05F3/02
CPC分类号： G05F3/205
摘要： In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.
摘要翻译：在一种形式中，电路具有偏置级，其具有用于接收输入信号的输入信号端子。该电路用驱动级修改输入信号以提供补码形式的输出信号。电路的驱动级中的驱动晶体管具有连接到负载的端子和耦合到输入信号端子的控制电极的体积。电路的偏置级中的偏置晶体管具有直接连接到负载的端子和驱动晶体管体的体积。偏置晶体管具有耦合到输入信号端子的控制电极。输入信号偏置驱动晶体管和偏置晶体管的体积，并降低晶体管阈值电压。电路输出阻抗的线性提高，RF干扰降低。还提供较低的电压操作。

8. 发明授权

US07268524B2 Voltage regulator with adaptive frequency compensation 有权
标题翻译：具有自适应频率补偿的稳压器
公开(公告)号：US07268524B2
公开(公告)日：2007-09-11
申请号：US10891811
申请日：2004-07-15
申请人： Kiyoshi Kase , May Len
发明人： Kiyoshi Kase , May Len
IPC分类号： G05F1/40
CPC分类号： G05F1/575
摘要： A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.
摘要翻译：电压调节器包括第一和第二放大器级，输出级和可变零电路。第一放大器级耦合以接收参考电压并引入电压调节器的第一极。第二放大器级耦合到第一放大器级并引入电压调节器的第二极。输出级耦合到第二放大器级，具有输出驱动器，并且被耦合以提供基于参考电压的输出电压。可变零电路耦合到第一放大器级，第二放大级和输出级。基于输出驱动器的栅极 - 源极电压和输出驱动器的漏极 - 源极电压，可变零电路提供零以补偿电压调节器的第一极点或第二极点中的至少一个极点。

9. 发明授权

US07002371B2 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US07002371B2
公开(公告)日：2006-02-21
申请号：US10747748
申请日：2003-12-29
申请人： Kiyoshi Kase , May Len , Dzung T. Tran
发明人： Kiyoshi Kase , May Len , Dzung T. Tran
IPC分类号： H03K19/094
CPC分类号： H03K17/102 , H03K3/356008 , H03K3/356113
摘要： A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.
摘要翻译：具有不同阈值电压的交叉耦合反相器的电平移位器。在上电期间，电平转换器的输出被拉到已知的电压状态。在一些示例中，一个反相器包括附加的N沟道晶体管，其中由于附加晶体管，阈值电压大于另一个反相器的阈值电压。

10. 发明申请

US20090160484A1 Input buffer 有权
标题翻译：输入缓冲区
公开(公告)号：US20090160484A1
公开(公告)日：2009-06-25
申请号：US12004617
申请日：2007-12-21
申请人： Kiyoshi Kase , May Len , Dzung T. Tran
发明人： Kiyoshi Kase , May Len , Dzung T. Tran
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.
摘要翻译：用于缓冲输入信号的方法和相应系统包括响应于输入信号低于较低阈值输出第一逻辑值。响应于输入信号上升到较低阈值以上而输出第二逻辑值。此后，维持第二逻辑值，直到输入超过较高阈值，然后低于较高阈值。响应于输入信号低于较高阈值，第一逻辑值被输出并保持在第一逻辑值，直到输入低于低阈值，然后上升到低于下阈值。

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