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1. 发明申请

US20140061565A1 NONVOLATILE MEMORY 有权
标题翻译：非易失性存储器
公开(公告)号：US20140061565A1
公开(公告)日：2014-03-06
申请号：US13687737
申请日：2012-11-28
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , H01L27/2481 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/1675
摘要： A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.
摘要翻译：根据实施例的非易失性存储器包括第一布线; 布置在所述第一布线之上并沿与所述第一布线相交的方向延伸的第二布线; 以及电阻变化层，其布置在所述第一布线与所述第二布线的交叉区域中，所述第二布线包括沿着所述第二布线延伸的方向延伸的第一构件和包含布置在所述第二布线上的金属元件的电极层第一构件的沿着第二布线延伸的方向的侧表面，电极层的下表面与电阻变化层的上表面接触。

2. 发明申请

US20080173916A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20080173916A1
公开(公告)日：2008-07-24
申请号：US12016431
申请日：2008-01-18
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： G11C11/34 , H01L29/78
CPC分类号： H01L29/7883 , G11C13/0009 , H01L27/115 , H01L27/2463 , H01L29/42324 , H01L29/42328 , H01L29/512 , H01L45/085 , H01L45/1206 , H01L45/142 , H01L45/143
摘要： A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
摘要翻译：半导体存储器件的写入和擦除方法包括具有半导体衬底的浮栅型晶体管，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极和与浮置栅极相对的控制栅电极夹着中空部的栅电极。在半导体衬底和控制栅电极之间的电容通过在空心部分中形成电连接浮栅电极和控制栅电极的电路以及消除电路的操作之一来控制。

3. 发明申请

US20130248803A1 MOLECULAR MEMORY AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：分子记忆及其制备方法
公开(公告)号：US20130248803A1
公开(公告)日：2013-09-26
申请号：US13601200
申请日：2012-08-31
申请人： Kiyohito NISHIHARA , Tetsuya HAYASHI
发明人： Kiyohito NISHIHARA , Tetsuya HAYASHI
IPC分类号： H01L45/00
CPC分类号： H01L45/142 , G11C13/0014 , G11C13/0016 , G11C2213/71 , G11C2213/79 , H01L45/1608 , H01L51/0591
摘要： According to one embodiment, a molecular memory includes a first electrode, a second electrode, and a resistance-change molecular chain provided between the first electrode and the second electrode. The first electrode includes a core made of a first conductive material, and a side wall made of a second conductive material different from the first conductive material. The side wall is formed on a side surface of the core. The second electrode is made of a third conductive material different from the first conductive material. The resistance-change molecular chain is bonded to the first conductive material.
摘要翻译：根据一个实施例，分子存储器包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化分子链。第一电极包括由第一导电材料制成的芯和由与第一导电材料不同的第二导电材料制成的侧壁。侧壁形成在芯的侧表面上。第二电极由不同于第一导电材料的第三导电材料制成。电阻变化分子链与第一导电材料结合。

4. 发明申请

US20120211861A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120211861A1
公开(公告)日：2012-08-23
申请号：US13225743
申请日：2011-09-06
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L27/115 , H01L21/768 , H01L21/762
CPC分类号： H01L27/11524 , H01L21/76229 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators are formed in an upper layer portion of the semiconductor substrate. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.
摘要翻译：根据一个实施例，半导体存储器件包括半导体衬底，多个元件分离绝缘体和触点。多个元件分离绝缘体形成在半导体衬底的上层部分中。多个元件分离绝缘体将上层部分分成沿第一方向延伸的多个有效区域。触点连接到活动区域。在每个有源区域的上表面的第一方向上的部分中形成凹部。在与第一方向正交的第二方向上在整个有源区域上形成凹部。在相互相邻的有源区域分别连接的两个触点的第一方向上的位置彼此不同。触点之一与凹部的侧表面接触并且不与凹部的底表面接触。

5. 发明申请

US20110049604A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110049604A1
公开(公告)日：2011-03-03
申请号：US12839723
申请日：2010-07-20
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L29/788
CPC分类号： H01L21/76819 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11565 , H01L27/11568
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a semiconductor substrate; an element isolation insulator formed in an upper portion of the semiconductor substrate and dividing the upper portion into first and second active areas extending in a first direction; a first contact connected to the first active area; and a second contact connected to the second active area. Each of the first and second active area includes: a first portion connected to one of the first contact and the second contact; and a second portion having an upper surface being placed lower than an upper surface of the first portion. The first contact and the second contact are mutually shifted in the first direction. The first portion of the first active area is disposed adjacent to the second portion of the second active area.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括：半导体衬底; 形成在所述半导体衬底的上部并将所述上部分割成沿第一方向延伸的第一和第二有源区的元件绝缘绝缘体; 连接到第一活动区域的第一触点; 以及连接到第二活动区域的第二触点。第一和第二有效区域中的每一个包括：连接到第一接触件和第二接触件之一的第一部件; 以及第二部分，其具有比第一部分的上表面低的上表面。第一触点和第二触点在第一方向相互移位。第一有效区域的第一部分被布置成与第二有效区域的第二部分相邻。

6. 发明申请

US20130015518A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20130015518A1
公开(公告)日：2013-01-17
申请号：US13353818
申请日：2012-01-19
申请人： Hiroyasu SATO , Kiyohito NISHIHARA , Hidefumi NAWATA , Masayuki ICHIGE , Ryuji OHBA
发明人： Hiroyasu SATO , Kiyohito NISHIHARA , Hidefumi NAWATA , Masayuki ICHIGE , Ryuji OHBA
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/764 , H01L27/11524 , H01L29/40114 , H01L29/42336 , H01L29/66825
摘要： In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion.
摘要翻译：通常，根据一个实施例，半导体存储器件包括在第一方向上延伸的有源区域，设置在有源区域上的隧道膜，设置在隧道膜上的浮置栅极电极，设置在浮动栅电极上并延伸的电极间绝缘膜在第二方向上，设置在电极间绝缘膜上并沿第二方向延伸的控制栅电极，设置在有源区之间，隧道膜之间以及在第二方向相邻的浮栅之间的下绝缘部分，以及设置在下绝缘部和电极间绝缘膜之间的上绝缘部。下绝缘部分包括空隙。上绝缘部分的相对介电常数高于下绝缘部分的相对介电常数。电极间绝缘膜的相对介电常数高于上绝缘部分。

7. 发明申请

US20110012185A1 SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20110012185A1
公开(公告)日：2011-01-20
申请号：US12889848
申请日：2010-09-24
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , G11C13/0009 , H01L27/115 , H01L27/2463 , H01L29/42324 , H01L29/42328 , H01L29/512 , H01L45/085 , H01L45/1206 , H01L45/142 , H01L45/143
摘要： A write and erase method of a semiconductor memory device includes a floating gate type transistor having a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, and a control gate electrode opposing the floating gate electrode with a hollow portion being sandwiched therebetween. A capacitance between the semiconductor substrate and the control gate electrode is controlled by one of an operation of forming, in the hollow portion, an electrical path which electrically connects the floating gate electrode and the control gate electrode, and an operation of eliminating the electrical path.
摘要翻译：半导体存储器件的写入和擦除方法包括具有半导体衬底的浮栅型晶体管，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的浮置栅电极和与浮置栅极相对的控制栅电极夹着中空部的栅电极。在半导体衬底和控制栅电极之间的电容通过在空心部分中形成电连接浮栅电极和控制栅电极的电路以及消除电路的操作之一来控制。

8. 发明申请

US20100140213A1 APPARATUS FOR MANUFACTURING CARBON NANO TUBES AND METHOD OF SORTING CARBON NANO TUBES 审中-公开
标题翻译：用于制造碳纳米管的装置和分配碳纳米管的方法
公开(公告)号：US20100140213A1
公开(公告)日：2010-06-10
申请号：US12618039
申请日：2009-11-13
申请人： Makoto MIZUKAMI , Kiyohito NISHIHARA
发明人： Makoto MIZUKAMI , Kiyohito NISHIHARA
IPC分类号： B44C1/22 , B05D3/00 , B03C1/00
CPC分类号： B03C1/08 , B03C1/24 , B03C2201/20 , B03C2201/26 , B82Y30/00 , B82Y40/00 , C01B32/172 , C01B2202/22
摘要： An apparatus for manufacturing carbon nano tubes of an aspect of the present invention including an introducing unit commonly introducing a first carbon nano tube having first magnetic characteristics and a second carbon nano tube having second magnetic characteristics different from the first magnetic characteristics, first and second collecting units collecting the first and second carbon nano tubes, respectively, a transport unit transporting the first and second carbon nano tubes from the introducing unit to the first and second collecting units, and at least one of a magnetic field generating unit which is provided adjacent to the transport unit and applies a magnetic field to the first and second carbon nano tubes, wherein the first carbon nano tube and the second carbon nano tube are sorted by the magnetic field generating unit.
摘要翻译：本发明的一个方面的碳纳米管的制造装置，其特征在于，包括通常导入具有第一磁特性的第一碳纳米管的导入部和具有与第一磁特性不同的第二磁特性的第二碳纳米管，第一和第二收集分别收集第一和第二碳纳米管的传送单元，其将第一和第二碳纳米管从引入单元传送到第一和第二收集单元;以及至少一个磁场产生单元，所述输送单元对所述第一和第二碳纳米管施加磁场，其中所述第一碳纳米管和所述第二碳纳米管由所述磁场产生单元分选。

9. 发明申请

US20100117134A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100117134A1
公开(公告)日：2010-05-13
申请号：US12562558
申请日：2009-09-18
申请人： Kiyohito NISHIHARA
发明人： Kiyohito NISHIHARA
IPC分类号： H01L27/105 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L29/40117 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film.
摘要翻译：在由单晶硅制成的硅衬底上形成电介质膜，在电介质膜中形成开口，在电介质膜上形成非晶硅膜，非晶硅膜通过开口与硅衬底接触，使该非晶硅膜的固相外延生长从硅衬底开始，然后进行图案化。由此，在从开口的正上方偏离的区域的一部分形成由单晶硅构成的种子层。接下来，沉积非晶硅膜以覆盖种子层，通过从种子层开始的非晶硅膜的固相外延生长形成单晶硅膜。通过图案化单晶硅膜形成硅柱。

10. 发明申请

US20090003071A1 SEMICONDUCTOR STORAGE DEVICE AND READ VOLTAGE CORRECTION METHOD 审中-公开
标题翻译：半导体存储器件和读取电压校正方法
公开(公告)号：US20090003071A1
公开(公告)日：2009-01-01
申请号：US11850390
申请日：2007-09-05
申请人： Kiyohito NISHIHARA , Fumitaka Arai
发明人： Kiyohito NISHIHARA , Fumitaka Arai
IPC分类号： G11C16/06
CPC分类号： H01L27/105 , G11C16/0483 , G11C16/26 , G11C16/3427 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/11526
摘要： A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.
摘要翻译：半导体存储器件包括：半导体存储器，存储通过校正半导体存储器的读取电压产生的校正电压的校正电压存储电路;以及从校正后的电压存储电路读取校正电压并进行读取操作的存储器控制器的半导体存储器。

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