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    • 7. 发明申请
    • POSITIVE DISPLACEMENT FLUID FLOW METER
    • 积极位移流体流量计
    • US20100300199A1
    • 2010-12-02
    • US11990169
    • 2006-08-10
    • Ian Holmes HigginIan YoungIvor Rogers
    • Ian Holmes HigginIan YoungIvor Rogers
    • G01F3/08
    • G01F3/08
    • A positive displacement fluid flow meter comprises a chamber having a fluid inlet and a fluid outlet. A rotor is displaceable within the chamber, rotation of the rotor being related to the volume of fluid passing through the chamber. The chamber has a surface proximate which an end surface of the rotor passes, the chamber surface and/or the rotor end surface having at least one recess to retain at least a portion of debris carried by the metered fluid. The recess is preferably formed so as not to provide fluid, communication, from the inlet to the outlet across the rotor end surface. A lid closes an end of the chamber which in use is subject to the pressure of fluid within the chamber. The lid is engaged at its periphery to a wall of the chamber, and is preferably flexible adjacent its periphery to reduce the transmission of bending stresses between the periphery of the lid and the remainder thereof.
    • 正排量流体流量计包括具有流体入口和流体出口的室。 转子可在腔室内移动,转子的旋转与通过腔室的流体体积相关。 腔室具有靠近转子的端表面的表面,腔室表面和/或转子端表面具有至少一个凹部以保持由计量流体携带的碎屑的至少一部分。 凹部优选地形成为不使流体从转子端表面的入口到出口提供流体。 盖子封闭了腔室的一端,在使用过程中受到室内流体的压力的影响。 盖子在其周边处接合到室的壁上,并且优选地邻近其周边是柔性的,以减小盖的周边与其余部分之间的弯曲应力的传递。
    • 9. 发明授权
    • Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication
    • 低功耗,低相位抖动和占空比误差不敏感的时钟接收器架构和电路用于源同步数字数据通信
    • US07501869B2
    • 2009-03-10
    • US11592594
    • 2006-11-03
    • Yongping FanIan Young
    • Yongping FanIan Young
    • H03L7/06
    • H03L7/0812H03L7/07H03L7/0805H03L7/0891
    • A clock receiver architecture for source synchronous digital data communication, the receiver including a forwarded clock amplifier to provide the received forwarded clock signal to a plurality of delay locked loops. Each delay locked loops provides to one or more phase interpolators a set of clock signals generated from the received forwarded clock, where the relative phases of the set of clock signals are uniformly spaced. Phase interpolators interpolate between two adjacent (with respect to phase) clock signals so as to provide a clock signal to sample received data at the center of the data eye. In some embodiments, an on-die voltage regulator provides a regulated supply voltage to the delay locked loops and phase interpolators. In some embodiments, pull-up currents and pull-down currents in the phase locked loops and phase interpolators are matched across process, supply voltage, and temperature variations so that the relative phases of the clock signals are insensitive across process, supply voltage, and temperature variations. Other embodiments are described and claimed.
    • 一种用于源同步数字数据通信的时钟接收器架构,接收器包括转发的时钟放大器,以将接收到的转发时钟信号提供给多个延迟锁定环路。 每个延迟锁定环路向一个或多个相位内插器提供从接收的转发时钟生成的一组时钟信号,其中该组时钟信号的相对相位是均匀间隔的。 相位插值器在两个相邻(相对于相位)时钟信号之间插值,以便提供一个时钟信号来对数据眼睛中心的接收数据进行采样。 在一些实施例中,片上电压调节器向延迟锁定环路和相位内插器提供稳定的电源电压。 在一些实施例中,锁相环和相位内插器中的上拉电流和下拉电流在过程,电源电压和温度变化之间匹配,使得时钟信号的相对相位在过程,电源电压和 温度变化。 描述和要求保护其他实施例。