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1. 发明授权

US5392250A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5392250A
公开(公告)日：1995-02-21
申请号：US5219
申请日：1993-01-15
申请人： Kinya Mitsumoto , Yoshikazu Iida , Hiroki Miyashita , Kazunori Onozawa
发明人： Kinya Mitsumoto , Yoshikazu Iida , Hiroki Miyashita , Kazunori Onozawa
IPC分类号： G11C11/417 , G11C11/409 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00 , G11C11/40
CPC分类号： G11C11/419 , H01L27/11
摘要： In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.
摘要翻译：在本发明的半导体存储器件中，从存储单元读取到一对互补数据线或一对公共数据线的数据直接通过任何读出放大器直接馈送到输出电路。结果，使用读出放大器的传统半导体存储器件的地址访问时间省略了读出放大器本身的延迟时间，使得本发明的半导体存储器件可以使其地址访问时间缩短比传统的半导体存储器件。

2. 发明授权

US5290714A Method of forming semiconductor device including a CMOS structure having double-doped channel regions 失效
标题翻译：形成半导体器件的方法包括具有双掺杂沟道区的CMOS结构
公开(公告)号：US5290714A
公开(公告)日：1994-03-01
申请号：US941825
申请日：1992-09-08
申请人： Kazunori Onozawa
发明人： Kazunori Onozawa
IPC分类号： H01L21/8238 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L21/265
CPC分类号： H01L21/8249 , H01L21/823807 , H01L27/0623 , H01L27/0928 , Y10S148/009
摘要： A semiconductor device has, in one embodiment, a p type insulated gate field effect transistor formed in an n type well formed on a semiconductor substrate and an n type insulated gate field effect transistor formed in a p type well formed on the semiconductor substrate. Each of the p type and n type insulated gate-field effect transistors has a composite impurity layer under its gate electrode in a surface portion of its associated well. The composite impurity layer includes a first doped layer of a p type and a second doped layer of an n type adjacent thereto to form a pn junction layer therebetween, while the composite impurity layer includes a first doped layer of a p type and a second doped layer of a p type adjacent thereto to form a junction layer therebetween having a p type impurity concentration lower than that of the p type well.
摘要翻译：在一个实施例中，半导体器件具有形成在形成在半导体衬底上的n型阱中的p型绝缘栅场效应晶体管和形成在p型阱上的n型绝缘栅场效应晶体管，形成在半导体衬底上。 p型和n型绝缘栅场效应晶体管中的每一个在其相关阱的表面部分中具有在其栅电极下方的复合杂质层。复合杂质层包括第一掺杂层和第二掺杂层，其中n型相邻以在其间形成pn结层，而复合杂质层包括第一掺杂层ap型和第二掺杂层 ap型，以形成其p型杂质浓度低于p型阱的p型阱的结层。

3. 发明授权

US5903036A Semiconductor device having MISFET SRAM cells in which active regions and gate electrodes are dimensioned for increasing storage node capacitances without increasing memory cell size 失效
标题翻译：具有MISFET SRAM单元的半导体器件，其中有源区和栅电极的尺寸用于增加存储节点电容而不增加存储单元尺寸
公开(公告)号：US5903036A
公开(公告)日：1999-05-11
申请号：US820247
申请日：1997-03-18
申请人： Kazunori Onozawa
发明人： Kazunori Onozawa
IPC分类号： H01L27/11 , H01L21/8244 , H01L27/112
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903
摘要： A semiconductor device is constituted by an arrangement of MISFET type SRAM cells structured such that near the edge of active regions of the driver MISFETs in each memory cell, at least one of the source and drain regions of each driver MISFET is offset against the gate electrode of that MISFET. This offset structure is formed by implantation of impurities using a mask covering the edge proximity of the active regions. Moreover, near one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the gate length of that driver MISFET is at least twice the gate length of the MISFET which has the shortest gate length and which constitutes part of a memory cell or a peripheral circuit. Also, at one edge of the gate electrode of each driver MISFET in an SRAM memory cell, the spacing distance between the gate electrode of that driver MISFET and the gate electrode (word line) of a transfer MISFET is made substantially the same in at least two directions. Also, the spacing distance between the gate electrode of each driver MISFET and the gate electrode of a corresponding driver MISFET in an adjacent memory cell is made substantially the same as the spacing distance between the gate electrode of each driver MISFET and the gate electrode (word line) of the transfer MISFET connected thereto.
摘要翻译：半导体器件由MISFET型SRAM单元的结构构成，其结构使得在每个存储单元中的驱动器MISFET的有源区的边缘附近，每个驱动器MISFET的源极和漏极区中的至少一个偏置于栅电极的MISFET。该偏移结构通过使用覆盖有源区域的边缘附近的掩模注入杂质来形成。而且，在SRAM存储单元中的每个驱动器MISFET的栅电极的一个边缘附近，该驱动器MISFET的栅极长度至少是具有最短栅极长度并且构成存储单元的一部分的MISFET的栅极长度的两倍或外围电路。此外，在SRAM存储单元中的每个驱动器MISFET的栅电极的一个边缘处，该驱动器MISFET的栅电极与转移MISFET的栅电极（字线）之间的间隔距离至少基本上相同两个方向此外，每个驱动器MISFET的栅电极与相邻存储单元中相应的驱动器MISFET的栅电极之间的间隔距离与每个驱动器MISFET的栅电极和栅电极（字）之间的间隔距离基本相同线）连接到其上的传输MISFET。

4. 发明授权

US4990461A Method of making a semiconductor integrated circuit device having resistance elements 失效
标题翻译：制造具有电阻元件的半导体集成电路器件的方法
公开(公告)号：US4990461A
公开(公告)日：1991-02-05
申请号：US386696
申请日：1989-07-31
申请人： Kazunori Onozawa
发明人： Kazunori Onozawa
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/732
CPC分类号： H01L27/11801 , H01L27/0629
摘要： A semiconductor integrated circuit device having resistance elements having reduced fluctuation of their resistance values and a fabrication method thereof are disclosed.More definitely, a protective film made of a gate electrode material of MISFETs formed on the main plane of a semiconductor substrate is disposed through an insulator film on the upper surface of the resistance elements comprising a semiconductor region which is formed by introducing an impurity of a first conductivity type into the main plane of the same semiconductor substrate.
摘要翻译：公开了具有电阻值波动减小的电阻元件的半导体集成电路器件及其制造方法。更确定地说，在半导体衬底的主平面上形成的由MISFET形成的栅极材料制成的保护膜通过绝缘膜设置在电阻元件的上表面上，该电阻元件包括半导体区域，该半导体区域是通过引入第一导电类型进入同一半导体衬底的主平面。

5. 发明授权

US4868626A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4868626A
公开(公告)日：1989-09-19
申请号：US044202
申请日：1987-04-30
申请人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
发明人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0623 , Y10S257/903
摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
摘要翻译：半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

6. 发明授权

US4672416A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4672416A
公开(公告)日：1987-06-09
申请号：US843614
申请日：1986-03-25
申请人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
发明人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/73 , H01L29/732 , H01L27/02
CPC分类号： H01L27/0623 , Y10S257/903
摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
摘要翻译：半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

7. 发明授权

US5847434A Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5847434A
公开(公告)日：1998-12-08
申请号：US642699
申请日：1996-05-03
申请人： Kazunori Onozawa
发明人： Kazunori Onozawa
IPC分类号： H01L27/10 , H01L21/8249 , H01L27/06 , H01L27/105 , H01L21/225
CPC分类号： H01L21/8249 , H01L27/0635 , H01L27/105 , Y10S257/903
摘要： A semiconductor integrated circuit device is provided which includes a memory cell M, in which a capacitance element C is added to the storage node portion of an inverter circuit composed of a drive MOSFET and a load TFT Qf. The device also includes and a bipolar transistor Tr provided as a peripheral element. A reference power supply line to be connected with the source region of the drive MOSFET Qd and an emitter electrode to be connected with the emitter region of the bipolar transistor Tr are formed of an uppermost thick polycrystal silicon film. Moreover, an intermediate thin polycrystal silicon film between the uppermost polycrystal silicon film and a first polycrystal silicon film (or polycide film) is covered in a memory cell forming region with the uppermost polycrystal silicon film. Still moreover, the uppermost polycrystal silicon film is partially silicified.
摘要翻译：提供了一种半导体集成电路器件，其包括存储单元M，其中将电容元件C添加到由驱动MOSFET和负载TFT Qf组成的反相器电路的存储节点部分。该器件还包括作为外围元件提供的双极晶体管Tr。与驱动MOSFET Qd的源极区域连接的基准电源线和与双极晶体管Tr的发射极区域连接的发射极电极由最上层的多晶硅膜形成。此外，在最上面的多晶硅膜和第一多晶硅膜（或多晶硅膜）之间的中间薄多晶硅膜被覆盖在具有最上面的多晶硅膜的存储单元形成区域中。此外，最上面的多晶硅膜被部分硅化。

8. 发明授权

US5722285A Caliper sensor 失效
标题翻译：卡尺传感器
公开(公告)号：US5722285A
公开(公告)日：1998-03-03
申请号：US688434
申请日：1996-07-30
申请人： Akihiko Tsuchiya , Yutaka Saito , Kazunori Onozawa
发明人： Akihiko Tsuchiya , Yutaka Saito , Kazunori Onozawa
IPC分类号： G01B7/06 , G01B7/00
CPC分类号： G01B7/107
摘要： A caliper sensor of the opposing contact type, wherein are provided target supporting spherical surfaces comprising at least three spherical surfaces disposed on a periphery of a target facing plane of a sliding surface and a plane determined by the tops of each spherical surface and in contact in parallel with a measurement reference plane above the target; and contact spherical surfaces for the reference plane outside the target facting plane of the sliding surface, whose number is equal to or greater than that of the relevant target supporting spherical surfaces and the tops of each spherical surface having a height about equal to the relevant target supporting spherical surfaces, so that contaminants are steered away from the tops of the spherical surfaces and the measurement process is thereby unaffected by the contaminants for a long period of time.
摘要翻译：相对接触型的卡尺传感器，其中设置有目标支撑球面，其包括设置在滑动表面的目标面对平面的周边上的至少三个球形表面和由每个球形表面的顶部确定并且接触的平面与目标上方的测量参考平面平行; 并且将滑动表面的目标实际平面外的参考平面的球面接触，其数量等于或大于相关的目标支撑球形表面的顶点，并且每个球形表面的顶部具有大约等于相关目标的高度支撑球形表面，使得污染物从球形表面的顶部转向远离，并且测量过程由此不被污染物长时间影响。

9. 发明授权

US5029323A Semiconductor device 失效
公开(公告)号：US5029323A
公开(公告)日：1991-07-02
申请号：US399952
申请日：1989-08-29
申请人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
发明人： Shinji Nakazato , Hideaki Uchida , Nobuo Tanba , Nobuyuki Gotoo , Kazunori Onozawa , Atsushi Hiraishi
IPC分类号： H01L27/082 , H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L29/73 , H01L29/732
CPC分类号： H01L27/0623 , Y10S257/903
摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

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