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1. 发明授权

US4998155A Radiation-hardened semiconductor device with surface layer 失效
标题翻译：具有表面层的辐射硬化半导体器件
公开(公告)号：US4998155A
公开(公告)日：1991-03-05
申请号：US73305
申请日：1987-07-13
申请人： Kikuo Watanabe , Tohru Nakamura , Toru Toyabe , Takahiro Okabe , Minoru Nagata
发明人： Kikuo Watanabe , Tohru Nakamura , Toru Toyabe , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L29/73 , H01L21/331 , H01L29/08 , H01L29/10 , H01L29/72 , H01L29/732
CPC分类号： H01L29/1008 , H01L29/1004 , H01L29/72 , Y10S257/906
摘要： A radiation-hardened semiconductor device including a bipolar transistor is disclosed in which a highly-doped layer equal in conductivity type to and larger in impurity concentration than the base region of the transistor is formed in that portion of the surface of the base region which exists beneath an insulating film, to prevent minority carriers injected into the base region, from reaching the above-mentioned surface portion. Thus, the injected minority carriers can reach a collector region without being extinguished by the recombination at the surface of the base region.
摘要翻译：公开了一种包括双极晶体管的辐射硬化半导体器件，其中在存在的基极区域的表面部分中形成了与晶体管的基极区相比导电类型等于或大于杂质浓度的高掺杂层在绝缘膜下面，以防止注入基底区域的少数载流子到达上述表面部分。因此，注入的少数载流子可以到达集电极区，而不会被基区表面的复合所熄灭。

2. 发明授权

US4429326A I.sup.2 L Memory with nonvolatile storage 失效
标题翻译： I2L带非易失性存储器的内存
公开(公告)号：US4429326A
公开(公告)日：1984-01-31
申请号：US96388
申请日：1979-11-21
申请人： Tomoyuki Watanabe , Kenji Kaneko , Tohru Nakamura , Yutaka Okada , Takahiro Okabe , Minoru Nagata , Yokichi Itoh , Toru Toyabe
发明人： Tomoyuki Watanabe , Kenji Kaneko , Tohru Nakamura , Yutaka Okada , Takahiro Okabe , Minoru Nagata , Yokichi Itoh , Toru Toyabe
IPC分类号： G11C11/411 , G11C14/00 , G11C16/04 , H01L27/02 , H01L27/07 , H01L27/102 , G11C11/40 , H01L27/04 , H01L29/78 , H03K19/091
CPC分类号： H01L27/0711 , G11C11/4113 , G11C14/00 , G11C16/0433 , G11C16/0466 , H01L27/0233 , H01L27/1022
摘要： An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.
摘要翻译：本发明的I2L型非易失性存储器具有这样的结构，其中浮置栅极通过I2L中的NPN晶体管的基极区附近的半导体层的表面上的绝缘膜设置。本发明的I2L型非易失性存储器通过要存储在浮动栅极中的电荷来控制电流流过I2L的NPN晶体管的基极区域。也就是说，I2L的NPN晶体管的集电极输出电流根据浮置栅极下面的通道的存在或不存在而被调制，这取决于浮置栅极内的电荷的存在或不存在以及浮置栅极的极性收费。结果，基极电流的变化在I2L的NPN晶体管的集电极端子处显示为输出信号，并且可以读出存储在浮动栅极中的数据。

3. 发明授权

US4825281A Bipolar transistor with sidewall bare contact structure 失效
标题翻译：双极晶体管与侧壁裸接触结构
公开(公告)号：US4825281A
公开(公告)日：1989-04-25
申请号：US435552
申请日：1982-10-21
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735 , H01L23/48 , H01L29/04 , H01L29/34
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
摘要翻译：一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面的绝缘膜基本上均匀。

4. 发明授权

US4258379A IIL With in and outdiffused emitter pocket 失效
标题翻译： IIL带有进出口的发射器口袋
公开(公告)号：US4258379A
公开(公告)日：1981-03-24
申请号：US78452
申请日：1979-09-24
申请人： Tomoyuki Watanabe , Takahiro Okabe , Minoru Nagata , Tohru Nakamura , Kenji Kaneko , Yutaka Okada , Norio Anzai , Takanori Nishimura , Takashi Agatsuma
发明人： Tomoyuki Watanabe , Takahiro Okabe , Minoru Nagata , Tohru Nakamura , Kenji Kaneko , Yutaka Okada , Norio Anzai , Takanori Nishimura , Takashi Agatsuma
IPC分类号： H01L21/74 , H01L21/761 , H01L21/8226 , H01L27/02 , H01L27/04 , H03K19/091
CPC分类号： H01L21/74 , H01L21/761 , H01L21/8226 , H01L27/0244
摘要： A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.
摘要翻译：一种在P型半导体衬底中形成N型半导体层的半导体IC器件; N型层被P +型绝缘区划分成多个岛状区域; 并且在第一岛状区域中形成IIL，而在第二岛状区域中形成NPN晶体管，其中N型上扩散层从第一岛区的底部向上形成，而N型阱区为从第一岛区域的表面向下形成，并且在第一岛区域和第二岛区域的底部附近形成N +型掩埋层。

5. 发明授权

US4933737A Polysilon contacts to IC mesas 失效
标题翻译：多晶硅接触到IC台面
公开(公告)号：US4933737A
公开(公告)日：1990-06-12
申请号：US56127
申请日：1987-06-01
申请人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
发明人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
IPC分类号： H01L21/20 , H01L21/285 , H01L21/331 , H01L21/8226 , H01L23/532 , H01L27/02 , H01L27/06 , H01L27/082 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/73
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02532 , H01L21/02546 , H01L21/28525 , H01L23/53271 , H01L27/0233 , H01L27/06 , H01L29/1004 , H01L29/42304 , H01L29/456 , H01L29/7317 , H01L2924/0002 , Y10S438/965
摘要： A bipolar transistor comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinsic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.
摘要翻译：双极晶体管包括具有凸部的n型Si半导体本体，覆盖半导体主体的除凸部以外的表面的绝缘膜以及形成在绝缘膜上的p型多晶Si层。形成在凸部中的p型区域作为本征基极区域，多晶Si层用作非本征基极区域，在本征基极区域中形成的n型区域用作发射极区域，并且主体用作一个收集区域。

6. 发明授权

US4258330A Differential current amplifier 失效
标题翻译：差分电流放大器
公开(公告)号：US4258330A
公开(公告)日：1981-03-24
申请号：US12028
申请日：1979-02-14
申请人： Kenji Kaneko , Takahiro Okabe , Tohru Nakamura , Wasao Takasugi , Minoru Nagata
发明人： Kenji Kaneko , Takahiro Okabe , Tohru Nakamura , Wasao Takasugi , Minoru Nagata
IPC分类号： H03F3/45 , H03K5/24 , H03K19/018 , H03K19/091
CPC分类号： H03K19/091 , H03F3/4508 , H03K19/01818 , H03K5/2409 , H03F2203/45344 , H03F2203/45394 , H03F2203/45674
摘要： A differential amplifier circuit wherein one collector of the multicollector of each of first, second and third inverse NPN transistors is connected to a base of the corresponding transistor; the first and second transistors are used as differential input transistors; the other collector of each of the first and second transistors is connected to a PNP transistor serving as a load current source; and an output is derived through the third transistor connected to the second transistor.
摘要翻译：一种差分放大器电路，其中第一，第二和第三反向NPN晶体管中的每一个的多极集电极的一个集电极连接到相应晶体管的基极; 第一和第二晶体管用作差分输入晶体管; 第一和第二晶体管中的每一个的另一个集电极连接到用作负载电流源的PNP晶体管; 并且通过连接到第二晶体管的第三晶体管导出输出。

7. 发明授权

US5061645A Method of manufacturing a bipolar transistor 失效
公开(公告)号：US5061645A
公开(公告)日：1991-10-29
申请号：US498489
申请日：1990-03-26
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

8. 发明授权

US5019523A Process for making polysilicon contacts to IC mesas 失效
标题翻译：使多晶硅接触到IC台面的工艺
公开(公告)号：US5019523A
公开(公告)日：1991-05-28
申请号：US501964
申请日：1990-03-30
申请人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
发明人： Tohru Nakamura , Takao Miyazaki , Susumu Takahashi , Ichiro Imaizumi , Takahiro Okabe , Minoru Nagata , Masao Kawamura
IPC分类号： H01L21/20 , H01L21/285 , H01L21/331 , H01L21/8226 , H01L23/532 , H01L27/02 , H01L27/06 , H01L27/082 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/73
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02532 , H01L21/02546 , H01L21/28525 , H01L23/53271 , H01L27/0233 , H01L27/06 , H01L29/1004 , H01L29/42304 , H01L29/456 , H01L29/7317 , H01L2924/0002 , Y10S438/965
摘要： Disclosed is a process for making a bipolar transistor which comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A p-type region formed in the convex portion serves as an intrinsic base region, the polycrystalline Si layer serves as an extrinic base region, an n-type region formed in the intrinsic base region serves as an emitter region, and the body serves as a collector region.

9. 发明授权

US4589096A IIL semiconductor memory including arrangement for preventing information loss during read-out 失效
标题翻译： IIL半导体存储器包括用于在读出期间防止信息丢失的装置
公开(公告)号：US4589096A
公开(公告)日：1986-05-13
申请号：US476269
申请日：1983-03-17
申请人： Kenji Kaneko , Takahiro Okabe , Minoru Nagata
发明人： Kenji Kaneko , Takahiro Okabe , Minoru Nagata
IPC分类号： G11C11/411 , G11C11/416 , H01L21/8229 , H01L27/102 , G11C11/00
CPC分类号： G11C11/416 , G11C11/4113 , H01L27/1025
摘要： A semiconductor memory having memory cells in each of which emitter terminals and first collector terminals of two IIL unit circuits are cross-connected to each other, injector regions and a common emitter region of the two IIL unit circuits are respectively connected to upper and lower word lines, and second collectors of the IIL unit circuits are respectively connected to a pair of bit lines that are respectively connected through load elements to a power source higher in voltage than the lower word line. This serves to hold the bit line potential higher than the lower word line potential to ensure that transistors formed by the second collectors, the emitters and the bases are inversely operated to prevent information loss during a read operation.
摘要翻译：具有存储单元的半导体存储器，其中两个IIL单元电路的发射极端子和第一集电极端子彼此交叉连接，两个IIL单元电路的喷射器区域和公共发射极区域分别连接到上部和下部单元线路和IIL单元电路的第二集电极分别连接到分别通过负载元件连接到电压高于下字线的电源的一对位线。这用于将位线电位保持为高于低字线电位，以确保由第二集电极，发射极和基极形成的晶体管反向操作，以防止读操作期间的信息丢失。

10. 发明授权

US4433258A Complementary Schottky transistor logic circuit 失效
标题翻译：互补肖特基晶体管逻辑电路
公开(公告)号：US4433258A
公开(公告)日：1984-02-21
申请号：US245163
申请日：1981-03-18
申请人： Kenji Kaneko , Takahiro Okabe , Minoru Nagata , Yutaka Okada
发明人： Kenji Kaneko , Takahiro Okabe , Minoru Nagata , Yutaka Okada
IPC分类号： H03K19/082 , H03K19/091 , H03K19/092 , H03K19/088
CPC分类号： H03K19/0915 , H03K19/082
摘要： A logic circuit is provided which includes a plurality of basic circuits each of which has a pnp (or npn) transistor as a constant current load and at least one npn (or pnp) transistor each as a driver with a clamping Schottky diode. The base of the driver transistor is used as an input terminal and the collector thereof is used as an output terminal, for each basic circuit and the output terminal of the preceding stage basic circuit is coupled directly to the input terminal of the subsequent stage basic circuit. In order to prevent current hogging the load current supplied from the preceding stage constant current load transistor is set to operate the subsequent stage driver transistor in a saturation made when the subsequent stage driver transistor is in the ON state.
摘要翻译：提供了一种逻辑电路，其包括多个基本电路，每个基本电路具有作为恒定电流负载的pnp（或npn）晶体管和每个具有钳位肖特基二极管的驱动器的至少一个npn（或pnp）晶体管）。驱动晶体管的基极用作输入端子，其集电极用作输出端子，对于每个基本电路，前级基本电路的输出端子直接耦合到后级基本电路的输入端子。为了防止电流偏移，设定从前一级恒流负载晶体管提供的负载电流，以使后级级驱动晶体管处于导通状态时产生的饱和度使后级级驱动晶体管工作。

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