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1. 发明授权

US06292060B1 Technique to generate negative conductance in CMOS tuned cascode RF amplifiers 失效
标题翻译：在CMOS调谐共源共RF放大器中产生负电导的技术
公开(公告)号：US06292060B1
公开(公告)日：2001-09-18
申请号：US09395288
申请日：1999-09-13
申请人： Kiat-Seng Yeo , Kok Lim Chan , Manh Anh Do , Jian Guo Ma , Johnny Kok Wai Chew
发明人： Kiat-Seng Yeo , Kok Lim Chan , Manh Anh Do , Jian Guo Ma , Johnny Kok Wai Chew
IPC分类号： H03F3191
CPC分类号： H03F1/56 , H03F1/223 , H03F2200/294 , H03F2200/369 , H03F2200/372
摘要： In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.
摘要翻译：在本发明中，将单个附加电容器添加到调谐共源共栅LNA，其升高电路Q和放大器的增益。增加的电容产生阻抗的负实部，当与LC谐振电路的阻抗相结合时，可以提高放大器的Q和增益。电容器不会耗散任何电源，而作为无源器件，电容器不会对电路增加额外的噪声。随着改进的增益，信噪比有了很大改善。较高的Q允许放大器提供一些额外的带通，并降低后续放大器级中的图像降低要求。

2. 发明授权

US06521939B1 High performance integrated varactor on silicon 有权
标题翻译：硅片上高性能集成变容二极管
公开(公告)号：US06521939B1
公开(公告)日：2003-02-18
申请号：US09672764
申请日：2000-09-29
申请人： Kiat-Seng Yeo , Chun Qi Geng , Kok-Wai Chew , Manh-Anh Do , Jian Guo Ma
发明人： Kiat-Seng Yeo , Chun Qi Geng , Kok-Wai Chew , Manh-Anh Do , Jian Guo Ma
IPC分类号： H01L27108
CPC分类号： H01L29/94 , H01L27/0808 , H01L29/66181
摘要： A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.
摘要翻译：描述了一种新的MOS变容二极管装置。底部电极在半导体衬底中包括多个扩散结。半导体衬底可以是n型或p型。扩散结被排列成二维阵列。扩散结可以是n型或p型。扩散结可以包含在p阱或n阱中。电介质层覆盖在半导体衬底上。顶部电极覆盖在电介质层上。顶部电极包括单个多边形，其中包含其中的开口的二维阵列，其暴露扩散结。顶部电极优选包括多晶硅。层间电介质层覆盖上电极和扩散结。层间电介质层具有暴露下面的扩散结的接触开口的二维阵列。图案化金属层覆盖层间电介质层，并通过接触开口接触扩散接头。

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