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1. 发明申请

US20080165580A1 3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 有权
标题翻译： 3级非挥发性半导体存储器件及其驱动方法
公开(公告)号：US20080165580A1
公开(公告)日：2008-07-10
申请号：US12052666
申请日：2008-03-20
申请人： Ki-Tae PARK , Jung-Dal CHOI , Sung-Kyu JO
发明人： Ki-Tae PARK , Jung-Dal CHOI , Sung-Kyu JO
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

2. 发明申请

US20070025161A1 3-LEVEL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME 失效
标题翻译： 3级非挥发性半导体存储器件及其驱动方法
公开(公告)号：US20070025161A1
公开(公告)日：2007-02-01
申请号：US11460580
申请日：2006-07-27
申请人： Ki-Tae PARK , Jung-Dal CHOi , Sung-Kyu JO
发明人： Ki-Tae PARK , Jung-Dal CHOi , Sung-Kyu JO
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

3. 发明申请

US20100091571A1 NONVOLATILE MEMORY DEVICE WITH NAND CELL STRINGS 有权
标题翻译：具有NAND单元线的非易失性存储器件
公开(公告)号：US20100091571A1
公开(公告)日：2010-04-15
申请号：US12636980
申请日：2009-12-14
申请人： Ki-Tae PARK , Jung-Dal CHOI
发明人： Ki-Tae PARK , Jung-Dal CHOI
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/3418
摘要： A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.
摘要翻译：非易失性存储器件包括存储单元阵列，其中多个存储单元晶体管被分成多个擦除块。多个擦除块通过虚拟字线彼此分离。在多个块之一的擦除操作期间，以耦合禁止电压驱动将多个块中的一个与其它擦除块分开的虚拟字线。

4. 发明申请

US20090290421A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 审中-公开
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20090290421A1
公开(公告)日：2009-11-26
申请号：US12536450
申请日：2009-08-05
申请人： Ki-Tae PARK , Jung-Dal CHOI
发明人： Ki-Tae PARK , Jung-Dal CHOI
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C16/12 , G11C16/0483
摘要： A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
摘要翻译：公开了一种闪存器件及其编程方法。闪存器件包括由多个位线和多个字线相交的存储器单元的阵列。页面缓冲电路包括耦合到偶数虚拟位线和奇数虚拟位线的多个锁存器。页面缓冲器电路被配置为响应于选择电路将数据加载到存储器单元阵列中，该选择电路被构造为将至少一些位线电耦合到页缓冲器电路的多个锁存器。

5. 发明申请

US20080023747A1 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS ON MULTIPLE LAYERS 有权
标题翻译：具有多层记忆细胞的半导体存储器件
公开(公告)号：US20080023747A1
公开(公告)日：2008-01-31
申请号：US11777293
申请日：2007-07-13
申请人： Ki-Tae PARK , Jung-Dal CHOI , Jae-Sung SIM
发明人： Ki-Tae PARK , Jung-Dal CHOI , Jae-Sung SIM
IPC分类号： H01L29/76
CPC分类号： H01L27/11551 , G11C11/5621 , G11C16/0483 , G11C2211/5641 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.
摘要翻译：半导体存储器件包括具有包括第一选择晶体管，第二选择晶体管和串联连接在第一衬底的第一和第二选择晶体管之间的第一存储单元的至少一个串的第一衬底。半导体存储器件还包括具有至少一个串的第二衬底，该至少一个串包括串联连接在第二衬底的第一和第二选择晶体管之间的第一选择晶体管，第二选择晶体管和第二存储单元。第一衬底的至少一个串的第一存储器单元的数量与第二衬底的至少一个串的第二存储单元的数量不同。例如，第二存储器单元的数量可以小于第一存储器单元的数量。

6. 发明申请

US20090122622A1 LEVEL SHIFTER WITH REDUCED LEAKAGE CURRENT AND BLOCK DRIVER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：具有减少漏电流和非驱动半导体存储器件的块驱动器的电平变换器
公开(公告)号：US20090122622A1
公开(公告)日：2009-05-14
申请号：US12349692
申请日：2009-01-07
申请人： Ki-Tae PARK , Jung Dal CHOI
发明人： Ki-Tae PARK , Jung Dal CHOI
IPC分类号： G11C7/00
CPC分类号： H03K19/018521 , G11C16/08
摘要： A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal. The enable unit comprises; a shifting voltage terminal adapted to receive the boost voltage, a control node, a shifting unit disposed between the shifting voltage terminal and the control node and responsive to the output signal, such that a voltage having a difference with the boost voltage lower than a voltage of the output signal is provided to the control node, whereby the output signal is boosted by the positive boost voltage, a control PMOS transistor disposed between the control node and the output signal and gated by the input signal, and bulk voltage generation unit adapted to generate a predetermined bulk voltage having a voltage difference with the boost voltage lower than that of the control node to a bulk of the control PMOS transistor.
摘要翻译：公开了一种电平转换器，并且产生具有相对于输入信号偏移正升压电压的摆幅电压的输出信号。电平移位器包括：响应于所述输入信号使能所述输出信号的使能单元，以及适于响应于所述输入信号禁用所述输出信号的禁用单元。使能单元包括：适于接收升压电压的换档电压端子，控制节点，设置在变换电压端子和控制节点之间并响应于输出信号的移位单元，使得与升压电压的差值低于电压输出信号被提供给控制节点，由此输出信号由正升压电压升压，控制PMOS晶体管设置在控制节点和输出信号之间并由输入信号选通，体电压产生单元适于产生具有与控制节点的升压电压相比低于控制PMOS晶体管体积的电压差的预定体积电压。

7. 发明申请

US20140104917A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS 审中-公开
标题翻译：半导体存储器件，包括存储芯片的多样性
公开(公告)号：US20140104917A1
公开(公告)日：2014-04-17
申请号：US14108417
申请日：2013-12-17
申请人： Ki-Tae PARK
发明人： Ki-Tae PARK
IPC分类号： G11C8/12 , G11C5/02
CPC分类号： G11C8/12 , G11C5/02 , G11C5/025 , G11C5/143 , G11C7/20
摘要： A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips
摘要翻译：半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个设备芯片

8. 发明申请

US20090213661A1 NON-VOLATILE MEMORY DEVICE ADAPTED TO REDUCE COUPLING EFFECT BETWEEN STORAGE ELEMENTS AND RELATED METHODS 审中-公开
标题翻译：非易失性存储器件适用于降低存储元件之间的耦合效应及相关方法
公开(公告)号：US20090213661A1
公开(公告)日：2009-08-27
申请号：US12396147
申请日：2009-03-02
申请人： Ki-Tae PARK , Ki-Nam KIM , Yeong-Taek LEE
发明人： Ki-Tae PARK , Ki-Nam KIM , Yeong-Taek LEE
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/12 , G11C16/3427 , G11C2211/5621 , G11C2211/5642
摘要： A non-volatile semiconductor memory device comprises first and second sub-memory arrays and a strapping line disposed between the first and second sub-memory arrays. A programming operation of the first sub-memory array is performed by simultaneously applying a programming voltage to odd and even bit lines connected to memory cells within the first sub-memory array.
摘要翻译：非挥发性半导体存储器件包括第一和第二子存储器阵列和布置在第一和第二子存储器阵列之间的捆扎线。通过同时向连接到第一子存储器阵列内的存储单元的奇偶位线施加编程电压来执行第一子存储器阵列的编程操作。

9. 发明申请

US20120262975A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS 有权
标题翻译：半导体存储器件，包括存储芯片的多样性
公开(公告)号：US20120262975A1
公开(公告)日：2012-10-18
申请号：US13537321
申请日：2012-06-29
申请人： Ki-Tae PARK
发明人： Ki-Tae PARK
IPC分类号： G11C5/02
CPC分类号： G11C8/12 , G11C5/02 , G11C5/025 , G11C5/143 , G11C7/20
摘要： A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips
摘要翻译：半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个设备芯片

10. 发明申请

US20090180339A1 SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL ARRAY AND REPAIR METHOD THEREOF 有权
标题翻译：具有三维阵列的半导体存储器件及其修复方法
公开(公告)号：US20090180339A1
公开(公告)日：2009-07-16
申请号：US12336827
申请日：2008-12-17
申请人： Doo-Gon KIM , Ki-Tae PARK
发明人： Doo-Gon KIM , Ki-Tae PARK
IPC分类号： G11C29/00 , G11C17/16
CPC分类号： G11C29/808
摘要： A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
摘要翻译：非易失性存储器件包括三维（3D）单元阵列，列选择电路和熔丝块。 3D单元阵列包括位于对应的堆叠衬底层中的多个单元阵列，单元阵列共享位线。列选择电路选择包括在3D单元阵列中的存储单元。熔丝块控制列选择电路，以修复位于3D单元阵列中的多个冗余位线之一的有缺陷的列。

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