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1. 发明授权

US09754921B2 Stacked semiconductor apparatus, system and method of fabrication 有权
公开(公告)号：US09754921B2
公开(公告)日：2017-09-05
申请号：US14683195
申请日：2015-04-10
申请人： Ki-Tae Park , Kang-Wook Lee , Young-Don Choi , Yun-Sang Lee
发明人： Ki-Tae Park , Kang-Wook Lee , Young-Don Choi , Yun-Sang Lee
IPC分类号： H01L23/00 , H01L25/065 , H01L23/64 , G11C5/06 , H01L23/34 , H01L23/538
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/34 , H01L23/5384 , H01L23/64 , H01L24/17 , H01L2224/16 , H01L2224/1712 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1058 , H01L2924/09701 , H01L2924/14 , H01L2924/1434 , H01L2924/19106 , H01L2924/00
摘要： A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

2. 发明授权

US09691782B1 Non-volatile memory device 有权
公开(公告)号：US09691782B1
公开(公告)日：2017-06-27
申请号：US15388369
申请日：2016-12-22
申请人： Chul-jin Hwang , Bong-soon Lim , Ki-tae Park
发明人： Chul-jin Hwang , Bong-soon Lim , Ki-tae Park
IPC分类号： H01L27/115 , H01L27/11573 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L27/02
CPC分类号： H01L27/11573 , H01L27/0266 , H01L27/11565 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A non-volatile memory device includes a substrate, a memory cell array on the substrate, a plurality of bonding pads, and a pad circuit. The memory cell array includes a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate. The plurality of bonding pads are on at least part of an upper portion of the memory cell array. The plurality of bonding pads are configured to electrically connect the non-volatile memory device to an external device. The pad circuit is between the substrate and the memory cell array. The pad circuit is electrically connected to at least one of the plurality of bonding pads.

3. 发明授权

US09480152B2 Carrier tape for tab-package and manufacturing method thereof 有权
标题翻译：用于片状包装的载带及其制造方法
公开(公告)号：US09480152B2
公开(公告)日：2016-10-25
申请号：US13188882
申请日：2011-07-22
申请人： Tae Ki Hong , Han Mo Koo , Jun Young Lim , Ki Tae Park , Sang Ki Cho , Dae Sung Yoo
发明人： Tae Ki Hong , Han Mo Koo , Jun Young Lim , Ki Tae Park , Sang Ki Cho , Dae Sung Yoo
IPC分类号： H05K1/09 , H05K1/00 , H05K1/02 , H01L23/00 , H01L23/498
CPC分类号： H05K1/028 , H01L23/4985 , H01L24/50 , H01L2924/01029 , H01L2924/14
摘要： The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.
摘要翻译：本发明涉及一种制造TAB龙头的方法。该方法包括在基膜上形成具有输入/输出端子图案的电路图案区域，并且在具有用于露出基底膜的链轮孔的输送区域处形成曝光区域。因此，本发明提供一种TAB带，其通过基本上防止金属颗粒的产生而形成暴露区域，从而通过选择性地蚀刻和去除在 TAB带，并且具有链轮孔，并且通过在不具有通过蚀刻形成在其上的电路图案的预定区域部分地去除基底膜来防止短路。

4. 发明授权

US09030004B2 Stacked semiconductor apparatus, system and method of fabrication 有权
标题翻译：叠层半导体器件，系统和制造方法
公开(公告)号：US09030004B2
公开(公告)日：2015-05-12
申请号：US13659146
申请日：2012-10-24
申请人： Ki-Tae Park , Kang-Wook Lee , Young-Don Choi , Yun-Sang Lee
发明人： Ki-Tae Park , Kang-Wook Lee , Young-Don Choi , Yun-Sang Lee
IPC分类号： H01L23/538 , H01L23/34 , H01L23/64 , H01L25/065 , G11C5/06
CPC分类号： H01L25/0657 , G11C5/06 , H01L23/34 , H01L23/5384 , H01L23/64 , H01L24/17 , H01L2224/16 , H01L2224/1712 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1058 , H01L2924/09701 , H01L2924/14 , H01L2924/1434 , H01L2924/19106 , H01L2924/00
摘要： A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.
摘要翻译：公开了一种叠层半导体器件及其制造方法。该装置包括具有相似图形的连接元件的上半导体器件和下半导体器件。当堆叠连接时，所得到的多个半导体器件包括穿过堆叠的串行连接路径，并且还可以包括并联连接路径，背面安装的大部件和垂直热导管。

5. 发明申请

US20130253170A1 HYALURONIC ACID-PROTEIN CONJUGATE AND METHOD FOR PREPARING SAME 有权
标题翻译：羟丙酸蛋白结合物及其制备方法
公开(公告)号：US20130253170A1
公开(公告)日：2013-09-26
申请号：US13992988
申请日：2011-12-05
申请人： Sei Kwang Hahn , Jeong A. Yang , Seung Kyu Yoon , Won Hee Hur , Ki Tae Park , Hye Min Kim , Hyun Tae Jung
发明人： Sei Kwang Hahn , Jeong A. Yang , Seung Kyu Yoon , Won Hee Hur , Ki Tae Park , Hye Min Kim , Hyun Tae Jung
IPC分类号： C07K14/56
CPC分类号： C07K14/56 , A61K31/726 , A61K31/728 , A61K38/191 , A61K38/21 , A61K38/212 , A61K38/215 , A61K38/217 , A61K47/36 , A61K47/61 , C07K14/525 , C07K14/565 , C07K14/57 , C07K17/10
摘要： An HA-protein conjugate in which an HA-aldehyde derivative, in which an aldehyde group is introduced to a hyaluronic acid or a salt thereof, is conjugated to the N-terminus of a protein, and a method for preparing the same are provided. The HA-protein conjugate includes a protein drug exhibiting an excellent bioconjugation efficiency and long-term medicinal effects, and has excellent protein drug activities since the hyaluronic acid is specifically conjugated to the N-terminus of the protein. Also, since liver-targeting properties of the hyaluronic acid can be freely controlled by changing an aldehyde substitution rate of the HA-aldehyde derivative, the HA-protein conjugate can be effectively used as a protein drug for treating liver diseases, and also be useful in enabling long-term medicinal effects of a protein drug required to bypass the liver. Accordingly, the HA-protein conjugate can be effectively used for a drug delivery system of proteins.
摘要翻译：提供其中将醛基引入透明质酸或其盐的HA-醛衍生物与蛋白质的N末端缀合的HA-蛋白质缀合物及其制备方法。 HA蛋白结合物包括显示出优异的生物共轭效率和长期药用作用的蛋白质药物，并且由于透明质酸与蛋白质的N末端特异性缀合，因此具有优异的蛋白质药物活性。此外，由于可以通过改变HA醛衍生物的醛取代率来自由地控制透明质酸的肝靶向性，因此HA蛋白结合物可以有效地用作治疗肝脏疾病的蛋白质药物，并且也是有用的能够使旁路肝脏所需的蛋白质药物具有长期的药效。因此，HA蛋白结合物可以有效地用于蛋白质的药物递送系统。

6. 发明授权

US08498160B2 Nonvolatile memory device and related programming method using selective bit line precharging 有权
标题翻译：非易失性存储器件和使用选择性位线预充电的相关编程方法
公开(公告)号：US08498160B2
公开(公告)日：2013-07-30
申请号：US12793007
申请日：2010-06-03
申请人： Bo Geun Kim , Ki tae Park
发明人： Bo Geun Kim , Ki tae Park
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C7/1048 , G11C16/0483 , G11C16/24 , G11C16/3454 , G11C2211/5621
摘要： A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops.
摘要翻译：非易失性存储器件的编程方法包括通过在某些程序循环的程序验证操作期间执行具有位线预充电的多个程序循环来编程存储器单元，并且在某些程序循环的程序验证操作期间激活位线预充电。

7. 发明授权

US08318856B2 Nucleic acid delivery system comprising conjugates of PEI and hyaluronic acid 有权
标题翻译：包含PEI和透明质酸的缀合物的核酸递送系统
公开(公告)号：US08318856B2
公开(公告)日：2012-11-27
申请号：US12733061
申请日：2008-04-04
申请人： Yu-Kyoung Oh , Hyun-Gu Kang , Ji-Seok Kim , Jiang Ge , Ki-Su Kim , Ki-Tae Park , Su-Eun Han , Ga-Yong Shim , Ii-Hwan Cho , Sei-Kwang Hahn
发明人： Yu-Kyoung Oh , Hyun-Gu Kang , Ji-Seok Kim , Jiang Ge , Ki-Su Kim , Ki-Tae Park , Su-Eun Han , Ga-Yong Shim , Ii-Hwan Cho , Sei-Kwang Hahn
IPC分类号： C08B37/00 , C08G63/48 , C08G63/91 , A61K48/00
CPC分类号： A61K47/61 , A61K47/59
摘要： The present invention relates to a delivery system for nucleic acid using a cationic polymer conjugate, and more specifically relates to a delivery system for nucleic acid comprising a cationic polymer conjugate prepared by conjugating hyaluronic acid or its derivative and polyethyleneimine, and a composition of delivering a nucleic acid into mammalian cell comprising a complex of the nucleic acid and a cationic polymer conjugate with electrostatic binding.
摘要翻译：本发明涉及使用阳离子聚合物缀合物的核酸递送系统，并且更具体地涉及用于核酸的递送系统，其包含通过将透明质酸或其衍生物和聚乙烯亚胺缀合而制备的阳离子聚合物缀合物，以及递送核酸进入哺乳动物细胞，其包含核酸和具有静电结合的阳离子聚合物缀合物的复合物。

8. 发明授权

US08014201B2 Nonvolatile memory device extracting parameters and nonvolatile memory system including the same 有权
标题翻译：非易失性存储器件提取参数和非易失性存储器系统包括相同的
公开(公告)号：US08014201B2
公开(公告)日：2011-09-06
申请号：US12458398
申请日：2009-07-10
申请人： Ki-Tae Park
发明人： Ki-Tae Park
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C8/12 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C2013/0083
摘要： The nonvolatile memory device includes a memory cell array having a plurality of memory blocks and a control logic circuit configured to store a parameter to access at least one of the plurality of memory blocks, configured to detect a variation of the parameter while accessing the at least one the memory block, and configured to store the varied parameter into the memory cell array in accordance with a result of the detection, wherein the control logic circuit is configured to utilize the varied parameter, which is stored in the memory cell array, while accessing the at least one memory block.
摘要翻译：非易失性存储器件包括具有多个存储器块的存储单元阵列和被配置为存储参数以访问多个存储器块中的至少一个的控制逻辑电路，其被配置为在至少访问至少一个存储器块时检测参数的变化一个存储块，并且被配置为根据检测结果将变化的参数存储到存储单元阵列中，其中控制逻辑电路被配置为利用存储在存储单元阵列中的变化的参数，同时访问所述至少一个存储器块。

9. 发明申请

US20110164445A1 SEMICONDUCTOR MEMORY DEVICE INCLUDING PLURALITY OF MEMORY CHIPS 有权
标题翻译：半导体存储器件，包括存储芯片的多样性
公开(公告)号：US20110164445A1
公开(公告)日：2011-07-07
申请号：US13052439
申请日：2011-03-21
申请人： Ki-Tae PARK
发明人： Ki-Tae PARK
IPC分类号： G11C5/02
CPC分类号： G11C8/12 , G11C5/02 , G11C5/025 , G11C5/143 , G11C7/20
摘要： A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips
摘要翻译：半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个设备芯片

10. 发明申请

US20110090738A1 NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME 有权
标题翻译：具有存储单元的NAND闪速存储器件及其操作方法
公开(公告)号：US20110090738A1
公开(公告)日：2011-04-21
申请号：US12977419
申请日：2010-12-23
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

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