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    • 2. 发明授权
    • External compensation for input current source
    • 输入电流源的外部补偿
    • US07911262B2
    • 2011-03-22
    • US12413596
    • 2009-03-29
    • Phat TruongPauline MaiChia-Jen Chang
    • Phat TruongPauline MaiChia-Jen Chang
    • G05F1/10G05F3/02
    • H03K19/00384
    • An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.
    • 集成电路包括:预驱动器级,耦合到外部电源电压,用于控制最终的驱动级; 耦合到预驱动器级和外部电源电压的最终驱动器级,用于提供输出电压; 耦合到预驱动器级的补偿电路,用于向前驱动器级提供偏置电压,其补偿外部电源电压的变化,以控制通过前驱动器级的电流; 以及耦合到外部电源电压和补偿电路的偏置电路,用于提供偏置电压作为对补偿电路的输入。
    • 3. 发明授权
    • OCD driver slew rate control
    • OCD驱动器转换速率控制
    • US07737728B1
    • 2010-06-15
    • US12413603
    • 2009-03-30
    • Phat TruongPauline Mai
    • Phat TruongPauline Mai
    • H03K19/094
    • H03K17/164H03K19/00361H03K19/00369
    • An off-chip driver (OCD) includes: a logic circuit, for providing a logic signal input; a pre-driver stage, coupled to the logic circuit, for providing a ramped up voltage in response to the logic signal input; a final driver stage, coupled to the pre-driver stage, for providing an output voltage in response to the ramped up voltage; and a bias circuit, coupled to the pre-driver stage, for providing a constant bias voltage to the pre-driver stage, wherein the constant bias voltage keeps the pre-driver stage within an operational range to compensate for variations in process, temperature and supply voltage.
    • 片外驱动器(OCD)包括:用于提供逻辑信号输入的逻辑电路; 耦合到所述逻辑电路的预驱动器级,用于响应于所述逻辑信号输入而提供斜升电压; 耦合到预驱动器级的最终驱动器级,用于响应于上升电压而提供输出电压; 以及耦合到所述预驱动器级的偏置电路,用于向所述预驱动器级提供恒定的偏置电压,其中所述恒定偏置电压将所述预驱动器级保持在操作范围内以补偿过程,温度和 电源电压。
    • 4. 发明申请
    • METHOD TO REDUCE VARIATION IN CMOS DELAY
    • 降低CMOS延迟变化的方法
    • US20090295466A1
    • 2009-12-03
    • US12129683
    • 2008-05-30
    • Phat TruongJon Nguyen
    • Phat TruongJon Nguyen
    • G05F1/10
    • G05F3/247
    • Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.
    • 提出了用于补偿由电源,温度和工艺变化引起的集成电路性能变化的控制电压电路。 控制电压电路包括串联连接的几个MOSFET晶体管,单位增益运算放大器和具有输入端子和输出端子的恒流源。 第一MOSFET的输入源极端子连接到恒流源和单位增益运算放大器。 电路的输出端子连接到CMOS延迟块。 为了补偿性能变化,单位增益运算放大器之前或之前的输出电压节点随着运行过程状态变慢或温度升高而偏移。 相反,当过程变得更快或者温度降低时,输出电压节点移动较低。
    • 7. 发明申请
    • SYNCHRONOUS SIGNAL GENERATING CIRCUIT
    • 同步信号发生电路
    • US20120212273A1
    • 2012-08-23
    • US13029949
    • 2011-02-17
    • Nhon NguyenPhat TruongJohn Phan
    • Nhon NguyenPhat TruongJohn Phan
    • H03H11/26H03K3/00
    • G11C7/222H03L7/0814H03L7/0816
    • A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.
    • 同步信号发生电路。 同步信号发生电路包括延迟锁定环(DLL),仿真器和复用器。 DLL用于根据计数值延迟参考时钟信号以产生第一输出时钟信号。 计数值根据第一输出时钟信号和参考时钟信号之间的相位差产生。 仿真器可操作以提供DLL的功能,并且包括可操作以接收参考时钟信号和参考计数值的可编程延迟线,其中参考时钟信号根据参考计数值被延迟以产生第二输出 时钟信号。 多路复用器可操作以接收第一和第二输出时钟信号并选择性地输出第一或第二输出时钟信号。 第一输出时钟信号以第一模式输出,第二输出时钟信号以第二模式输出。