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1. 发明授权

US09337138B1 Capacitors within an interposer coupled to supply and ground planes of a substrate 有权
标题翻译：插入器内的电容器耦合到衬底的电源和接地平面
公开(公告)号：US09337138B1
公开(公告)日：2016-05-10
申请号：US13416640
申请日：2012-03-09
申请人： Khaldoon S. Abugharbieh , Gregory Meredith , Christopher P. Wyland , Paul Y. Wu , Henley Liu , Sanjiv Stokes , Yong Wang
发明人： Khaldoon S. Abugharbieh , Gregory Meredith , Christopher P. Wyland , Paul Y. Wu , Henley Liu , Sanjiv Stokes , Yong Wang
IPC分类号： H01L23/52 , H01L23/522 , H01L23/66 , H01L49/02 , H01L23/498
CPC分类号： H01L23/5222 , H01L23/49822 , H01L23/5223 , H01L23/5385 , H01L23/642 , H01L23/66 , H01L24/16 , H01L28/40 , H01L2224/16227 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105
摘要： An embodiment of an apparatus to reduce supply voltage noise with capacitors of an interposer of a stacked die is disclosed. In this embodiment, an interposer is coupled to a first integrated circuit die using a first plurality of interconnects. A substrate is coupled to the interposer using a second plurality of interconnects. The substrate includes a supply voltage plane and a ground plane, each of which is coupled to the first integrated circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects. The interposer includes capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects, where capacitance from capacitors of the interposer is provided to the first integrated circuit die using the supply voltage plane and the ground plane of the substrate.
摘要翻译：公开了一种用于降低电源电压噪声的设备的实施例，该电容器具有堆叠管芯的插入器的电容器。在该实施例中，插入器使用第一多个互连件耦合到第一集成电路管芯。使用第二多个互连件将衬底耦合到插入器。基板包括电源电压平面和接地平面，每个基板使用第二多个互连，插入器和第一多个互连件耦合到第一集成电路管芯。插入器包括使用电源电压平面，接地平面和第二多个互连并联的电容器，其中使用电源电压平面和内插器的接地平面将插入器的电容器提供给第一集成电路管芯基质。

2. 发明授权

US08802454B1 Methods of manufacturing a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US08802454B1
公开(公告)日：2014-08-12
申请号：US13331702
申请日：2011-12-20
申请人： Arifur Rahman , Henley Liu , Cheang-Whang Chang , Myongseob Kim , Dong W. Kim
发明人： Arifur Rahman , Henley Liu , Cheang-Whang Chang , Myongseob Kim , Dong W. Kim
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L22/14
摘要： A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.
摘要翻译：提供了一种测试TSV的方法。在半导体衬底中形成多个TSV。布线层和第一接触阵列形成在基板的正面上。布线层将每个TSV耦合到第一接触阵列的相应触头。导电胶粘剂沉积在第一接触阵列上。导电粘合剂电耦合第一接触阵列的触点。载体用导电粘合剂粘合到基底的正面。在将载体接合到基板之后，将基板的背面变薄以使基板的背面上的每个TSV露出。形成第二接触阵列，其具有耦合到每个相应TSV的接触。通过测试第二接触阵列的触头之间的电导率来测试TSV，布线层和触点的电导率和连接。

3. 发明授权

US08354671B1 Integrated circuit with adaptive VGG setting 有权
标题翻译：具有自适应VGG设置的集成电路
公开(公告)号：US08354671B1
公开(公告)日：2013-01-15
申请号：US12781627
申请日：2010-05-17
申请人： Hsung Jai Im , Henley Liu , Jae-Gyung Ahn , Tony Le , Patrick J. Crotty
发明人： Hsung Jai Im , Henley Liu , Jae-Gyung Ahn , Tony Le , Patrick J. Crotty
IPC分类号： H01L23/58 , H01L29/10 , H01L21/66 , G01R31/26 , G01N27/00
CPC分类号： H01L22/34 , H01L29/42364
摘要： A technique for setting Vgg in an IC is disclosed. The technique includes specifying a design reliability lifetime for the IC, and a relationship between maximum gate bias and gate dielectric thickness for the IC sufficient to achieve the design reliability lifetime is established. The IC is fabricated and the gate dielectric thickness is measured. A maximum gate bias voltage is determined according to the gate dielectric thickness and the relationship between maximum gate bias and gate dielectric thickness, and a Vgg trim circuit of the IC is set to provide Vgg having the maximum gate bias voltage that will achieve the design reliability lifetime according to the measured gate dielectric thickness.
摘要翻译：公开了一种在IC中设置Vgg的技术。该技术包括指定IC的设计可靠性寿命，并建立足以实现设计可靠性寿命的IC的最大栅极偏置和栅极电介质厚度之间的关系。制造IC并测量栅介质厚度。根据栅极介电厚度和最大栅极偏置与栅极介质厚度之间的关系确定最大栅极偏置电压，并且设置IC的Vgg微调电路以提供具有最大栅极偏置电压的Vgg，其将实现设计可靠性根据测量的栅极介电厚度的寿命。

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