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1. 发明申请

US20050240810A1 Off-chip lockstep checking 有权
标题翻译：片外锁定检查
公开(公告)号：US20050240810A1
公开(公告)日：2005-10-27
申请号：US10818994
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis , Eric Delano
发明人： Kevin Safford , Donald Soltis , Eric Delano
IPC分类号： G06F11/00 , G06F11/16 , G06K19/067
CPC分类号： G06F11/1641 , G06F11/1625 , G06F2201/845
摘要： A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供了一种系统，其包括微处理器，该微处理器包括产生第一输出信号的第一处理单元和用于产生第二输出信号的第二处理单元，以及耦合到微处理器的比较装置，以检测第一输出信号是否与第二输出信号。

2. 发明申请

US20050108509A1 Error detection method and system for processors that employs lockstepped concurrent threads 审中-公开
标题翻译：使用锁定并发线程的处理器的错误检测方法和系统
公开(公告)号：US20050108509A1
公开(公告)日：2005-05-19
申请号：US10714093
申请日：2003-11-13
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F9/318 , G06F9/38 , G06F11/16 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30181 , G06F9/3863
摘要： A processor that includes an in-order execution architecture for executing at least two instructions per cycle (e.g., 2n instructions are processed per cycle, where n is an integer greater than or equal to one) and at least two symmetric execution units. The processor includes an instruction fetch unit for fetching n instructions (where n is an integer greater than or equal to one) and an instruction decoder for decoding the n instruction. The error detection mechanism includes duplication hardware for duplicating the n instructions into a first bundle of n instructions and a second bundle of n instructions. A first execution unit for executing the first bundle of instructions in a first execution cycle, and a second symmetric execution unit for executing the second bundle of instructions in the first execution cycle are provided. The error detection mechanism also includes comparison hardware for comparing the results of the first execution unit and the results of the second execution unit. The comparison hardware can have an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. A commit unit is provided for committing one of the results when the results are the same.
摘要翻译：一种处理器，其包括用于每个周期执行至少两个指令的按顺序执行架构（例如，每个周期处理2n个指令，其中n是大于或等于1的整数）和至少两个对称执行单元。处理器包括用于取出n个指令（其中n是大于或等于1的整数）的指令获取单元和用于对n指令进行解码的指令解码器。错误检测机制包括用于将n个指令复制到n个指令的第一束和第n个n个指令束中的复制硬件。提供了用于在第一执行周期中执行第一指令集的第一执行单元和用于在第一执行周期中执行第二指令集的第二对称执行单元。错误检测机构还包括用于比较第一执行单元的结果和第二执行单元的结果的比较硬件。当结果不相同时，比较硬件可以具有用于产生异常（例如，引起故障）的异常单元。当结果相同时，提交提交单元用于提交结果之一。

3. 发明申请

US20050138478A1 Error detection method and system for processors that employ alternating threads 审中-公开
标题翻译：使用交替线程的处理器的错误检测方法和系统
公开(公告)号：US20050138478A1
公开(公告)日：2005-06-23
申请号：US10714258
申请日：2003-11-14
申请人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
发明人： Kevin Safford , Donald Soltis , Stephen Undy , James Gibson , Eric Delano
IPC分类号： G06F11/14 , G06F11/00
CPC分类号： G06F11/1497 , G06F9/3861
摘要： Microprocessor that includes a mechanism for detecting soft errors. The processor includes an instruction fetch unit for fetching an instruction and an instruction decoder for decoding the instruction. The mechanism for detecting soft errors includes duplication hardware for duplicating the instruction and comparison hardware. The processor further includes a first execution unit for executing the instruction in a first execution cycle and the duplicated instruction in a second execution cycle. The comparison hardware compares the results of the first execution cycle and the results of the second execution cycle. The comparison hardware can include an exception unit for generating an exception (e.g., raising a fault) when the results are not the same. The processor also includes a commit unit for committing one of the results when the results are the same.
摘要翻译：微处理器，包括检测软错误的机制。处理器包括用于取出指令的指令获取单元和用于解码指令的指令解码器。用于检测软错误的机制包括用于复制指令和比较硬件的复制硬件。处理器还包括用于在第一执行周期中执行指令的第一执行单元和在第二执行周期中的复制指令。比较硬件比较第一个执行周期的结果和第二个执行周期的结果。当结果不相同时，比较硬件可以包括用于产生异常（例如，引起故障）的异常单元。处理器还包括提交单元，用于在结果相同时提交其中一个结果。

4. 发明申请

US20050240829A1 Lockstep error signaling 有权
标题翻译：锁步错误信号
公开(公告)号：US20050240829A1
公开(公告)日：2005-10-27
申请号：US10818993
申请日：2004-04-06
申请人： Kevin Safford , Eric Delano
发明人： Kevin Safford , Eric Delano
IPC分类号： G06F11/00 , G06F11/07 , G06F11/16
CPC分类号： G06F11/165 , G06F11/0724 , G06F11/0772 , G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： Techniques are disclosed, for use in a computer system including a plurality of processing units coupled over a system fabric, to identify a lockstep error associated with a first packet to be transmitted over the system fabric; set a viral indicator in the first packet to indicate the lockstep error; and transmit the modified packet over the system fabric.
摘要翻译：公开了用于包括通过系统结构耦合的多个处理单元的计算机系统中的技术，以识别与要在系统结构上传送的第一分组相关联的锁步错误; 在第一个数据包中设置病毒指示符，以指示锁步错误; 并通过系统结构传输修改的数据包。

5. 发明申请

US20050240793A1 Architectural support for selective use of high-reliability mode in a computer system 失效
标题翻译：在计算机系统中选择性使用高可靠性模式的架构支持
公开(公告)号：US20050240793A1
公开(公告)日：2005-10-27
申请号：US10819241
申请日：2004-04-06
申请人： Kevin Safford , Donald Soltis
发明人： Kevin Safford , Donald Soltis
IPC分类号： G06F9/30 , G06F11/00
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/3851 , G06F11/1629 , G06F2201/845
摘要： In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group without in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.
摘要翻译：在本发明的一个方面，提供一种电路，其实现定义第一指令组的指令集架构，进入高可靠性操作模式的第二指令组，以及进入非高速模式的第三指令组，可靠的运行模式。电路包括用于响应于接收到第二指令组而使电路进入高可靠性操作模式的装置; 响应于接收到第三指令组使电路进入非高可靠性操作模式的装置; 如果电路处于高可靠性操作模式，则在高可靠性操作模式下执行第一指令组的第一执行装置; 以及第二执行装置，用于如果电路处于非高可靠性操作模式，则在不处于非高可靠性操作模式的情况下执行第一指令组。

6. 发明申请

US20050240811A1 Core-level processor lockstepping 有权
标题翻译：核心级处理器锁步
公开(公告)号：US20050240811A1
公开(公告)日：2005-10-27
申请号：US10818975
申请日：2004-04-06
申请人： Kevin Safford , Christopher Lyles , Eric Delano
发明人： Kevin Safford , Christopher Lyles , Eric Delano
IPC分类号： G06F11/18 , G06F11/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1679 , G06F11/1641
摘要： A device is provided which includes a first microprocessor core to generate a first output signal; a second microprocessor core to generate a second output signal; a switching fabric having a first input/output port; and lockstep logic, coupled between the first input/output port of the switching fabric and the first and second microprocessor cores, to detect whether the first output signal differs from the second output signal.
摘要翻译：提供一种装置，其包括用于产生第一输出信号的第一微处理器核心; 第二微处理器核心，用于产生第二输出信号; 具有第一输入/输出端口的交换结构; 以及耦合在交换结构的第一输入/输出端口与第一和第二微处理器核心之间的锁步逻辑，以检测第一输出信号是否与第二输出信号不同。

7. 发明授权

US07409524B2 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US07409524B2
公开(公告)日：2008-08-05
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。这种VHPT高速缓存的引入消除或至少减少了在发生TLB缺失时微处理器在高速缓存层级或高速缓存之外的其他存储器（例如，主存储器）中寻找信息的需要，从而增强了微处理器速度。

8. 发明申请

US20070043929A1 System and method for responding to TLB misses 失效
标题翻译：用于响应TLB未命中的系统和方法
公开(公告)号：US20070043929A1
公开(公告)日：2007-02-22
申请号：US11205622
申请日：2005-08-17
申请人： Kevin Safford , Rohit Bhatia , Karl Brummel
发明人： Kevin Safford , Rohit Bhatia , Karl Brummel
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1018
摘要： The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.
摘要翻译：本发明涉及一种改进的微处理器，具有具有多个可以操作以提供虚拟存储器的高速缓存的存储器系统。在微处理器中包括的高速缓冲存储器中的是传统的高速缓冲存储器，其存储由微处理器执行的处理使用的数据和指令，并且通常被布置在高速缓存层级中，以及一个或多个转换后备缓冲器（TLB）高速缓存它存储有限数量的虚拟页面翻译。改进的微处理器还具有额外的高速缓存，用于存储当TLB未命中时被访问的虚拟散列页表（VHPT）。引入这种VHPT高速缓存消除或者至少减少了当TLB未命中时微处理器在高速缓存层级的高速缓存或微处理器外部的其他存储器（例如，主存储器）中查找信息的需要，从而增强了微处理器速度。

9. 发明申请

US20060036424A1 Method and apparatus for verifying resources shared by multiple processors 审中-公开
标题翻译：用于验证由多个处理器共享的资源的方法和装置
公开(公告)号：US20060036424A1
公开(公告)日：2006-02-16
申请号：US10917764
申请日：2004-08-13
申请人： Jeremy Petsinger , Danny Kwong , Kevin Safford
发明人： Jeremy Petsinger , Danny Kwong , Kevin Safford
IPC分类号： G06F13/10
CPC分类号： G06F9/52 , G06F12/084
摘要： Computer system models and methods for modeling computers that share resources are disclosed herein. One embodiment of the method for modeling a computer system comprises modeling a first shared resource and associating a first model of the first shared resource with a first processor model. A second model of the first shared resource is associated with a second processor model, wherein the first model of the first shared resource is substantially identical to the second model of the first shared resource. Data associated with the first model of the first shared resource is maintained to be equal to the data associated with the second model of the first shared resource.
摘要翻译：本文公开了用于建模共享资源的计算机的计算机系统模型和方法。用于建模计算机系统的方法的一个实施例包括对第一共享资源进行建模并将第一共享资源的第一模型与第一处理器模型相关联。第一共享资源的第二模型与第二处理器模型相关联，其中第一共享资源的第一模型基本上与第一共享资源的第二模型相同。与第一共享资源的第一模型相关联的数据被保持为等于与第一共享资源的第二模型相关联的数据。

10. 发明授权

US08479029B2 Methods and apparatuses for reducing step loads of processors 失效
公开(公告)号：US08479029B2
公开(公告)日：2013-07-02
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

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