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1. 发明申请

US20130275787A1 Methods And Apparatuses For Reducing Step Loads Of Processors 审中-公开
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20130275787A1
公开(公告)日：2013-10-17
申请号：US13913864
申请日：2013-06-10
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

2. 发明申请

US20090070607A1 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20090070607A1
公开(公告)日：2009-03-12
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

3. 发明申请

US20080234953A1 Power estimation for a semiconductor device 审中-公开
标题翻译：半导体器件的功率估计
公开(公告)号：US20080234953A1
公开(公告)日：2008-09-25
申请号：US11726819
申请日：2007-03-22
申请人： James S. Ignowski , Chris Bostak , Warren H. Parks
发明人： James S. Ignowski , Chris Bostak , Warren H. Parks
IPC分类号： G06F19/00
CPC分类号： G06F1/206 , G06F1/26 , Y02D10/16
摘要： Disclosed herein are different embodiments for estimating and/or controlling power consumption in a chip based on hot and cool temperatures in the chip.
摘要翻译：这里公开的是用于基于芯片中的热和冷温度估计和/或控制芯片中的功率消耗的不同实施例。

4. 发明授权

US08479029B2 Methods and apparatuses for reducing step loads of processors 失效
公开(公告)号：US08479029B2
公开(公告)日：2013-07-02
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

5. 发明申请

US20110252255A1 Methods And Apparatuses For Reducing Step Loads Of Processors 失效
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US20110252255A1
公开(公告)日：2011-10-13
申请号：US13167970
申请日：2011-06-24
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

6. 发明授权

US07992017B2 Methods and apparatuses for reducing step loads of processors 有权
标题翻译：减少处理器阶跃负载的方法和装置
公开(公告)号：US07992017B2
公开(公告)日：2011-08-02
申请号：US11900316
申请日：2007-09-11
申请人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
发明人： Kevin Safford , Rohit Bhatia , Chris Bostak , Richard Blumberg , Blaine Stackhouse , Steve Undy
IPC分类号： G06F1/32 , G06F11/30
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.
摘要翻译：公开了减少处理器的步进负载的方法和装置。方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并且将执行限制到指令的子集号码来控制执行期间的电量。一些实施例还可以创建人为活动以为处理器提供最小功率层。装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑的执行期间要处理的指令。

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