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1. 发明授权

US07051187B2 Superscalar RISC instruction scheduling 失效
公开(公告)号：US07051187B2
公开(公告)日：2006-05-23
申请号：US10086197
申请日：2002-03-01
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

2. 发明授权

US06289433B1 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US06289433B1
公开(公告)日：2001-09-11
申请号：US09329354
申请日：1999-06-10
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F1500
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependence check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括用于确定指令之间的数据依赖性的数据相关性检查电路。标签分配电路根据由数据相关性检查电路确定的数据相关性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

3. 发明授权

US07802074B2 Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US07802074B2
公开(公告)日：2010-09-21
申请号：US11730566
申请日：2007-04-02
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/38
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路基于由数据相关性检查电路确定的数据依赖性，生成一个或多个标签以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

4. 发明授权

US07555738B2 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip 失效
公开(公告)号：US07555738B2
公开(公告)日：2009-06-30
申请号：US11651467
申请日：2007-01-10
申请人： Kevin Ray Iadonato , Le Trong Nguyen
发明人： Kevin Ray Iadonato , Le Trong Nguyen
IPC分类号： G06F17/50 , G06F7/00 , G06F15/76 , G06F9/30 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F17/5068
摘要： An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

5. 发明授权

US07174525B2 Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip 失效
标题翻译：用于集成电路芯片的指令执行单元的集成结构布局和互连布局
公开(公告)号：US07174525B2
公开(公告)日：2007-02-06
申请号：US10885871
申请日：2004-07-08
申请人： Kevin Ray Iadonato , Le Trong Nguyen
发明人： Kevin Ray Iadonato , Le Trong Nguyen
IPC分类号： G06F17/50 , G06F17/76 , G06F7/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/30141 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F17/5068
摘要： An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
摘要翻译：用于集成电路芯片的功能块和互连的集成结构布局。数据依赖比较器块以行和列排列。这种布置定义行中相邻的数据依赖性比较器块之间的布局区域。标签分配逻辑块被耦合到数据依赖性比较器块以接收依赖性信息。标签分配逻辑块位于一个或多个布局区域中，以便与数据依赖性比较器块集成以节省半导体芯片上的区域，并在空间上定义在一个或多个行中并基本正交的通道。寄存器文件端口多路复用器块耦合到与正交信道相邻的标签分配逻辑块的输出线，以接收标签信息，并将标签信息传递到寄存器文件的地址端口。

6. 发明授权

US5974526A Superscalar RISC instruction scheduling 失效
标题翻译：超标量RISC指令调度
公开(公告)号：US5974526A
公开(公告)日：1999-10-26
申请号：US990414
申请日：1997-12-15
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路以确定指令之间的数据依赖性。标签分配电路根据由数据依赖性检查电路确定的数据依赖性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

7. 发明授权

US5737624A Superscalar risc instruction scheduling 失效
标题翻译：超标量risc指令调度
公开(公告)号：US5737624A
公开(公告)日：1998-04-07
申请号：US594401
申请日：1996-01-31
申请人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin Ray Iadonato , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependence check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括用于确定指令之间的数据依赖性的数据相关性检查电路。标签分配电路根据由数据相关性检查电路确定的数据相关性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

8. 发明授权

US07739482B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US07739482B2
公开(公告)日：2010-06-15
申请号：US11642599
申请日：2006-12-21
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F15/76
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

9. 发明授权

US07162610B2 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US07162610B2
公开(公告)日：2007-01-09
申请号：US10660671
申请日：2003-09-12
申请人： Le Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
发明人： Le Trong Nguyen , Derek J Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H Trang
IPC分类号： G06F15/78 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

10. 发明申请

US20050251653A1 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
公开(公告)号：US20050251653A1
公开(公告)日：2005-11-10
申请号：US11167289
申请日：2005-06-28
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： C10G1/00 , C10G17/02 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/76
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

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