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1. 发明授权

US07398373B2 System and method for processing complex computer instructions 有权
标题翻译：用于处理复杂计算机指令的系统和方法
公开(公告)号：US07398373B2
公开(公告)日：2008-07-08
申请号：US11392386
申请日：2006-03-29
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F15/00
CPC分类号： G06F9/3802 , G06F9/30174 , G06F9/328 , G06F9/382
摘要： A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instruction if it was.
摘要翻译：提供了一种处理复杂指令的系统和方法。该过程包括从可能嵌入在计算机指令中的地址生成跳转指令，并且如果不复杂则选择原始指令，如果是跳转指令则产生跳转指令。

2. 发明授权

US07162620B2 Methods and apparatus for multi-processing execution of computer instructions 有权
标题翻译：用于多处理执行计算机指令的方法和装置
公开(公告)号：US07162620B2
公开(公告)日：2007-01-09
申请号：US10202355
申请日：2002-07-24
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F15/80
CPC分类号： G06F15/8053 , A63F2300/203 , G06F9/325 , G06F9/3836 , G06F9/3885
摘要： A multi-processing computer architecture and a method of operating the same are provided. The multi-processing architecture provides a main processor and multiple sub-processors cascaded together to efficiently execute loop operations. The main processor executes operations outside of a loop and controls the loop. The multiple sub-processors are operably interconnected, and are each assigned by the main processor to a given loop iteration. Each sub-processor is operable to receive one or more sub-instructions sequentially, operate on each sub-instruction and propagate the sub-instruction to a subsequent sub-processor.
摘要翻译：提供了多处理计算机体系结构及其操作方法。多处理架构提供了主处理器和多个子处理器级联在一起以有效地执行循环操作。主处理器执行循环外的操作并控制循环。多个子处理器可操作地互连，并且由主处理器分配给给定的循环迭代。每个子处理器可操作以顺序地接收一个或多个子指令，对每个子指令进行操作，并将子指令传播到后续的子处理器。

3. 发明授权

US06961464B2 Method for creating a database such as a dictionary used for a word conversion system 有权
标题翻译：用于创建数据库的方法，例如用于字转换系统的字典
公开(公告)号：US06961464B2
公开(公告)日：2005-11-01
申请号：US10039546
申请日：2001-10-22
申请人： Hidetaka Magoshi , Nobuo Sasaki
发明人： Hidetaka Magoshi , Nobuo Sasaki
IPC分类号： G06F17/22 , G06F12/00 , G06F17/30 , G06F17/40 , G06K9/34
CPC分类号： G06F17/30616 , Y10S707/99943
摘要： Character (or letter) information is extracted from source information, word information is extracted from the character information, and a database is created of the word information. Thereby, the created database is adapted for the technical field of the user or a field of interest to the user.
摘要翻译：从源信息中提取字符（或字母）信息，从字符信息中提取字信息，并创建字信息的数据库。由此，所创建的数据库适用于用户的技术领域或用户感兴趣的领域。

4. 发明授权

US06816946B2 Methods and apparatus for controlling a cache memory 有权
标题翻译：用于控制高速缓冲存储器的方法和装置
公开(公告)号：US06816946B2
公开(公告)日：2004-11-09
申请号：US10187072
申请日：2002-07-01
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F1208
CPC分类号： G06F12/0875 , G06F12/0862
摘要： Methods and apparatus enable: the partitioning of a main memory into a plurality of blocks, each block being adjacent to at least one of the other blocks, and each block including a plurality of data units containing one or more bits of data; the partitioning of each block of the main memory into a plurality of zones, each zone containing one or more of the data units; the association of at least some of the respective zones of each given block with respective others of the adjacent blocks to the given block; and the pre-fetching of a given one of the other blocks into a cache memory when any one of the data units within any of the associated zones of that block is addressed.

5. 发明授权

US06341324B1 Exception processing in superscalar microprocessor 失效
标题翻译：超标量微处理器异常处理
公开(公告)号：US06341324B1
公开(公告)日：2002-01-22
申请号：US08540349
申请日：1995-10-06
申请人： Robert L. Caulk, Jr. , Hidetaka Magoshi , Kevin L. Daberkow
发明人： Robert L. Caulk, Jr. , Hidetaka Magoshi , Kevin L. Daberkow
IPC分类号： G06F1300
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/3861 , G06F9/3885
摘要： A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.
摘要翻译：微处理器系统包括用于指令执行的核心CPU和与所述核心CPU相互连接的用于系统控制和异常处理的协处理器。协处理器包括多个异常处理寄存器，其包括异常程序计数器，该异常程序计数器具有存储在其中的重新启动位置，用于在异常被服务之后使用，具有操作模式识别和中断使能位的状态寄存器以及配置和高速缓存控制寄存器。中断处理与通过设置配置和高速缓存控制寄存器中的至少一个比特指定的特定指令集的多个指令集兼容。提供寄存器以在中断使能之前保存CPU的工作状态，在完成异常处理并重新建立用户模式后恢复CPU的运行状态。

6. 发明授权

US07100023B2 System and method for processing complex computer instructions 有权
公开(公告)号：US07100023B2
公开(公告)日：2006-08-29
申请号：US09935878
申请日：2001-08-23
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F9/42
CPC分类号： G06F9/3802 , G06F9/30174 , G06F9/328 , G06F9/382
摘要： A system and method for handling complex instructions includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the Jump instruction if it was.

7. 发明授权

US06538957B2 Apparatus and method for distributing a clock signal on a large scale integrated circuit 有权
标题翻译：在大规模集成电路上分配时钟信号的装置和方法
公开(公告)号：US06538957B2
公开(公告)日：2003-03-25
申请号：US09929633
申请日：2001-08-14
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G11C700
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/1506 , H03L7/07 , H03L7/0814
摘要： A semiconductor chip includes a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each including a delay lock loop (DLL) circuit providing a DDL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of an Nth level subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the DDL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes are substantially coincident.
摘要翻译：半导体芯片包括位于半导体芯片上的多个区域时钟分配节点; 多个时钟缓冲器，每个时钟缓冲器包括提供DDL功能的延迟锁定环（DLL）电路，并且每个时钟缓冲器可操作以根据DLL功能从相关联的输入时钟信号产生相应的输出时钟信号，第N级的输出所述多个时钟缓冲器的子集耦合到所述多个区域时钟分配节点中的相应的时钟分配节点; 以及多个相位检测器，每个相位检测器可操作以产生指示至少两个区域时钟分配节点的输出时钟信号之间的相位差的相应误差信号，其中时钟缓冲器的第N个子集的DDL电路调整相应的根据相应的误差信号输出时钟信号，使得区域时钟分配节点的输出时钟信号基本一致。

8. 发明授权

US07870340B2 Methods and apparatus for controlling hierarchical cache memory 有权
标题翻译：用于控制分级缓存的方法和装置
公开(公告)号：US07870340B2
公开(公告)日：2011-01-11
申请号：US12290141
申请日：2008-10-28
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0864 , G06F12/0895 , G06F12/0897
摘要： Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.
摘要翻译：用于控制分级高速缓冲存储器存储器的方法和装置允许控制包括多条高速缓存行的第一级高速缓存存储器并且控制包括多条高速缓存行的下一级低速缓冲存储器。附加存储器可以与下一个较低级高速缓存存储器相关联，并且包括多个存储器线，存储线的数量对应于第一级高速缓冲存储器的方式集合中的高速缓存线的数量。或者，存储器线可以包括用于下一个较低级别高速缓存存储器的每一组的多个高速缓存行的L标志。与给定索引相关联的L标记加上来自第一级高速缓冲存储器的任何索引偏移可以包含在附加存储器的单个存储器行中。

9. 发明申请

US20060259787A1 Methods and apparatus for customizing a rewritable storage medium 有权
公开(公告)号：US20060259787A1
公开(公告)日：2006-11-16
申请号：US11488421
申请日：2006-07-18
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F12/14
CPC分类号： G06F21/79 , G06F21/10 , G06F2221/0744
摘要： Methods and apparatus permit: reading a rewritable storage medium, the rewritable storage medium including digital content and a flag indicative of whether the digital content is encrypted; determining whether the digital content of the rewritable storage medium is encrypted based on the flag; encrypting the digital content of the rewritable storage medium using an identification (ID) number as an encryption key when the flag indicates that the digital content is not encrypted, the ID number being unique to a processing apparatus operable to execute the digital content; and overwriting the digital content of the rewritable storage medium with the encrypted digital content.

10. 发明申请

US20060075193A1 Methods and apparatus for controlling hierarchical cache memory 有权
公开(公告)号：US20060075193A1
公开(公告)日：2006-04-06
申请号：US11290691
申请日：2005-11-30
申请人： Hidetaka Magoshi
发明人： Hidetaka Magoshi
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0848 , G06F12/0864 , G06F12/0895 , G06F12/0897
摘要： Methods and apparatus for controlling hierarchical cache memories permit controlling a first level cache memory including a plurality of cache lines and controlling a next lower level cache memory including a plurality of cache lines. An additional memory may be associated with the next lower level cache memory and include a plurality of memory lines, the number of memory lines corresponding to the number of cache lines in a way set of the first level cache memory. Alternatively, the memory lines may include L-flags for multiple cache lines of each way set of the next lower level cache memory. L-flags associated with a given index plus any index offset from the first level cache memory may be contained in a single memory line of the additional memory.

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