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1. 发明授权

US06287967B1 Self-aligned silicide process 失效
标题翻译：自对准硅化物工艺
公开(公告)号：US06287967B1
公开(公告)日：2001-09-11
申请号：US09451585
申请日：1999-11-30
申请人： Kevin Hsieh , Michael W C Huang , Wen-Yi Hsieh
发明人： Kevin Hsieh , Michael W C Huang , Wen-Yi Hsieh
IPC分类号： H01L2976
CPC分类号： H01L29/66515 , H01L29/41783 , H01L29/665
摘要： A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.
摘要翻译：自对准硅化物工艺。衬底至少形成有晶体管。在衬底上形成薄金属层。执行第一快速热处理以使金属层与栅极和源极/漏极区的多晶硅反应以形成第一金属硅化物层。去除不与多晶硅反应的金属层。执行选择性升高的自对准硅化物工艺以在第一金属硅化物层上形成第二金属硅化物层。执行第二快速热处理以将第一金属硅化物层和第二金属硅化物层从高电阻C49相转变成低电阻C54相。

2. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

3. 发明授权

US06307174B1 Method for high-density plasma etching 失效
标题翻译：高密度等离子体蚀刻方法
公开(公告)号：US06307174B1
公开(公告)日：2001-10-23
申请号：US09533036
申请日：2000-03-22
申请人： Chan-Lon Yang , Michael W C Huang , Tong-Yu Chen
发明人： Chan-Lon Yang , Michael W C Huang , Tong-Yu Chen
IPC分类号： B23K1000
CPC分类号： B23K10/00
摘要： A method for high-density plasma etching. A substrate is provided. A material layer is formed on the substrate. A patterned photo-resist layer is formed on the oxide layer. The material layer is patterned by the high-density plasma etching, simultaneously, a formation of a barrier layer over the substrate with the patterning process is suppressed and nitrogen gas generated in the patterned photo-resist layer is reduced.
摘要翻译：一种用于高密度等离子体蚀刻的方法。提供基板。在基板上形成材料层。在氧化物层上形成图案化的光刻胶层。通过高密度等离子体蚀刻来对材料层进行构图，同时，通过图案化工艺在衬底上形成阻挡层，并且在图案化光刻胶层中产生的氮气减少。

4. 发明授权

US06281143B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06281143B1
公开(公告)日：2001-08-28
申请号：US09334864
申请日：1999-06-17
申请人： Michael W C Huang , Hsueh-Hao Shih , Gwo-Shii Yang , Tri-Rung Yew
发明人： Michael W C Huang , Hsueh-Hao Shih , Gwo-Shii Yang , Tri-Rung Yew
IPC分类号： H01L2131
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/3143 , H01L21/321
摘要： A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.
摘要翻译：公开了一种形成无边界接触的方法。该方法包括提供具有有源区的衬底和沟槽隔离区，其中有源区是硅化物。然后，将衬底氮化，使得在有源区上形成氮化钛层，并在沟槽隔离区上形成氮氧化硅。介电层沉积在衬底上，并且在电介质层中蚀刻开口，其中开口覆盖沟槽隔离区的一部分和有源区的一部分。

5. 发明授权

US06235606B1 Method of fabricating shallow trench isolation 有权
标题翻译：浅沟槽隔离的制作方法
公开(公告)号：US06235606B1
公开(公告)日：2001-05-22
申请号：US09225031
申请日：1999-01-04
申请人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Kuo-Tai Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76224
摘要： A method for fabricating a shallow trench isolation. A pad oxide layer and a mask layer are formed over a substrate. The pad oxide layer, the mask layer, and the substrate are patterned to form a trench exposing a portion of the substrate. A liner oxide layer is formed on the substrate exposed by the trench. An isolation layer is formed over the substrate to cover the liner oxide layer. The isolation layer is conformal to the trench. An oxide layer is formed over the substrate to fill the trench. A portion of the oxide layer and the isolation layer is removed until the mask layer is exposed. The mask layer and the pad oxide layer are removed to form a shallow trench isolation.
摘要翻译：一种制造浅沟槽隔离的方法。在衬底上形成衬垫氧化物层和掩模层。将衬垫氧化物层，掩模层和衬底图案化以形成暴露衬底的一部分的沟槽。在由沟槽暴露的衬底上形成衬里氧化物层。在衬底上形成隔离层以覆盖衬里氧化物层。隔离层与沟槽保形。在衬底上形成氧化物层以填充沟槽。除去氧化物层和隔离层的一部分直到掩模层露出。去除掩模层和焊盘氧化物层以形成浅沟槽隔离。

6. 发明授权

US06218084B1 Method for removing photoresist layer 有权
公开(公告)号：US06218084B1
公开(公告)日：2001-04-17
申请号：US09212727
申请日：1998-12-15
申请人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
IPC分类号： G03F742
CPC分类号： H01L21/31138 , G03F7/427 , H01L21/31116
摘要： A method described for removing a photoresist/polymers layer on a substrate. The method comprises the steps of providing a wafer having an oxide layer, a photoresist/polymers layer, an opening penetrating through the photoresist/polymers layer and the oxide layer, and the sidewall polymer on the surface of photoresist layer and the oxide layer. An in-situ plasma-etching step using an additional gas mixed with oxygen as source is performed to remove the photoresist/polymers layer without residues, no damages to substrate and oxide and no changes on the critical dimension of the opening during etching step.

7. 发明授权

US06255023B1 Method of manufacturing binary phase shift mask 有权
标题翻译：制造二元相移掩模的方法
公开(公告)号：US06255023B1
公开(公告)日：2001-07-03
申请号：US09434046
申请日：1999-11-04
申请人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
发明人： Chien-Chao Huang , Michael W C Huang , Juan-Yuan Wu
IPC分类号： G03F900
CPC分类号： G03F1/32
摘要： A method of manufacturing a binary phase shift photomask. A phase shift layer and a mask layer are sequentially formed over a transparent substrate. The mask layer and the phase shift layer are patterned to form a plurality of first openings and a plurality of second openings that expose a portion of the transparent substrate. The mask layer is patterned to form a layer of mask material around the edges of the first openings. All first openings occupy an area greater than a preset minimum area while all second openings occupy an area greater than the preset minimum area. The mask layer only surrounds the first openings while the phase shift layer surrounds both the first and the second openings.
摘要翻译：一种制造二进制相移光掩模的方法。在透明基板上依次形成相移层和掩模层。图案化掩模层和相移层以形成多个第一开口和暴露透明基板的一部分的多个第二开口。图案化掩模层以在第一开口的边缘周围形成掩模材料层。所有第一开口占据大于预设最小面积的区域，而所有第二开口占据大于预设最小面积的区域。掩模层仅围绕第一开口，而相移层围绕第一和第二开口。

8. 发明授权

US06221712B1 Method for fabricating gate oxide layer 失效
标题翻译：栅极氧化层的制造方法
公开(公告)号：US06221712B1
公开(公告)日：2001-04-24
申请号：US09385805
申请日：1999-08-30
申请人： Kuo-Tai Huang , Michael W C Huang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Michael W C Huang , Tri-Rung Yew
IPC分类号： B32B1900
CPC分类号： H01L21/28194 , C23C16/405 , H01L21/28088 , H01L21/31604 , H01L29/4966 , H01L29/517
摘要： A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.
摘要翻译：一种用于制造栅极结构的方法。该方法包括提供衬底，随后在衬底的表面上形成氮化物区域。使用钽（Ta）基有机化合物和作为前体的钛（Ti）基有机化合物，进行有机金属化学气相沉积（OMCVD），从而在衬底上形成Ta2-xTixO5电介质层。然后依次在Ta2-xTixO5电介质层上形成阻挡层，导电层和抗反射（AR）层。随后，将AR层，导电层，阻挡层和Ta2-xTixO5电介质层定义为在氮化物区域的衬底上形成栅极结构。在这种情况下，Ta类有机化合物可以包括Ta-醇盐化合物，而Ti基有机化合物可以包括Ti-醇盐化合物或Ti-酰胺化合物。

9. 发明授权

US6140192A Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US6140192A
公开(公告)日：2000-10-31
申请号：US346554
申请日：1999-06-30
申请人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
发明人： Michael W C Huang , Hsiao-Ling Lu , Tri-Rung Yew
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/28247 , H01L29/665
摘要： A method for fabricating a semiconductor device. A substrate having a gate is provided. An ion implantation process is performed to form lightly doped source/drain region in the substrate. A liner layer and an insulation layer are formed over a substrate in sequence. A portion of the insulation layer is removed by an anisotropic etching process. The insulation layer remaining on sidewalls of the gate is used as a spacer. A top of the spacer is substantially level with an upper surface of the liner layer. An ion implantation process is performed to form heavily doped source/drain region in the substrate. A portion of the spacer is removed by wet etching. As a result, a top surface of the spacer is lower than the upper surface of the gate. The method can increase the exposed surface of the gate and maintain sufficient width of the lightly doped source/drain region to prevent the hot carrier effect and the short channel effect.
摘要翻译：一种半导体器件的制造方法。提供具有栅极的基板。执行离子注入工艺以在衬底中形成轻掺杂的源极/漏极区域。依次在衬底上形成衬垫层和绝缘层。通过各向异性蚀刻工艺去除绝缘层的一部分。留在栅极侧壁上的绝缘层用作间隔物。间隔件的顶部与衬里层的上表面基本一致。执行离子注入工艺以在衬底中形成重掺杂的源极/漏极区域。通过湿蚀刻去除间隔物的一部分。结果，间隔件的顶表面比门的上表面低。该方法可以增加栅极的暴露表面，并保持轻掺杂源极/漏极区域的足够宽度，以防止热载流子效应和短沟道效应。

10. 发明授权

US6139702A Seasoning process for etcher 有权
标题翻译：蚀刻机调味过程
公开(公告)号：US6139702A
公开(公告)日：2000-10-31
申请号：US263386
申请日：1999-03-05
申请人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Michael W C Huang
IPC分类号： C23C14/06 , C23C14/34 , H01L21/311 , G23C14/34
CPC分类号： C23C14/0682 , C23C14/3457 , H01L21/31116
摘要： A seasoning process for an etcher which is performed before etching a dielectric layer to expose a metal silicide layer. The seasoning process includes the first plasma sputtering process and the second plasma sputtering process. A wafer containing the metal silicide layer thereon is placed in the etcher with an etchant and the first plasma sputtering process is performed. Several silicon wafers are successively placed in the etcher to perform the second plasma sputtering process.
摘要翻译：在蚀刻介电层以暴露金属硅化物层之前执行的蚀刻器的调味过程。调味过程包括第一等离子体溅射工艺和第二等离子体溅射工艺。将含有其上的金属硅化物层的晶片用蚀刻剂放置在蚀刻器中，并且执行第一等离子体溅射工艺。将几个硅晶片依次放置在蚀刻器中以进行第二等离子体溅射工艺。

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