专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080016280A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING DATA CACHING AND DATA COMPRESSION IN A MEMORY SUBSYSTEM 失效
标题翻译：用于在存储器子系统中提供数据缓存和数据压缩的系统，方法和存储介质
公开(公告)号：US20080016280A1
公开(公告)日：2008-01-17
申请号：US11772922
申请日：2007-07-03
申请人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
发明人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
IPC分类号： G06F12/08
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
摘要翻译：包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

2. 发明申请

US20060095671A1 System, method and storage medium for providing data caching and data compression in a memory subsystem 失效
公开(公告)号：US20060095671A1
公开(公告)日：2006-05-04
申请号：US10977846
申请日：2004-10-29
申请人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
发明人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

3. 发明申请

US20080016281A1 SYSTEM, METHOD AND STORAGE MEDIUM FOR PROVIDING DATA CACHING AND DATA COMPRESSION IN A MEMORY SUBSYSTEM 有权
公开(公告)号：US20080016281A1
公开(公告)日：2008-01-17
申请号：US11780048
申请日：2007-07-19
申请人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
发明人： Kevin Gower , Mark Kellogg , Warren Maule , Thomas Smith , Robert Tremaine
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F12/0802 , G06F2212/401
摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

4. 发明申请

US20070286199A1 METHOD AND SYSTEM FOR PROVIDING IDENTIFICATION TAGS IN A MEMORY SYSTEM HAVING INDETERMINATE DATA RESPONSE TIMES 有权
标题翻译：在具有不确定性数据响应时间的记忆系统中提供识别标签的方法和系统
公开(公告)号：US20070286199A1
公开(公告)日：2007-12-13
申请号：US11843271
申请日：2007-08-22
申请人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
发明人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
IPC分类号： H04L12/56
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing identification tags in a memory system having indeterminate data response times. An exemplary embodiment includes a memory controller in a memory system. The memory controller includes a mechanism for receiving data packets via an upstream channel, the data packets including upstream identification tags. The memory controller also includes a mechanism having instructions for facilitating determining if a received data packet is in response to a request from the memory controller. Input to the determining includes an upstream identification tag included in the received data packet. If the received data packet is determined to be in response to a request from the memory controller, then the received data packet is matched to the request, thereby allowing the memory controller to operate with indeterminate data response times.
摘要翻译：一种用于在具有不确定的数据响应时间的存储器系统中提供识别标签的方法和系统。示例性实施例包括存储器系统中的存储器控制器。存储器控制器包括用于经由上游信道接收数据分组的机制，所述数据分组包括上行识别标签。存储器控制器还包括具有用于有助于确定接收的数据分组是否响应于来自存储器控制器的请求的指令的机制。确定的输入包括包含在接收的数据分组中的上游标识标签。如果接收到的数据分组被确定为响应于来自存储器控制器的请求，则接收的数据分组与该请求匹配，从而允许存储器控制器以不确定的数据响应时间进行操作。

5. 发明申请

US20070160053A1 Method and system for providing indeterminate read data latency in a memory system 失效
标题翻译：在存储器系统中提供不确定的读取数据延迟的方法和系统
公开(公告)号：US20070160053A1
公开(公告)日：2007-07-12
申请号：US11289193
申请日：2005-11-28
申请人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
发明人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.
摘要翻译：一种用于在存储器系统中提供不确定的读取数据等待时间的方法和系统。该方法包括确定是否已经接收到本地数据分组。如果接收到本地数据分组，则本地数据分组被存储到缓冲设备中。该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上行驱动器空闲。如果缓冲区包含数据包，并且上游驱动程序处于空闲状态，则将数据包传送到上游驱动程序。该方法还包括确定是否已经接收到上游数据分组。上行数据包是帧格式，包括帧开始指示符和存储器控制器在将上行数据包与其对应的读取指令相关联时使用的识别标签。如果已经接收到上游数据分组，并且上游驱动程序不空闲，则上游数据分组被存储到缓冲设备中。如果已经接收到上游数据分组，并且缓冲设备不包含数据分组，并且上游驱动器空闲，则将上游数据分组发送到上游驱动程序。如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

6. 发明申请

US20070183331A1 METHOD AND SYSTEM FOR PROVIDING INDETERMINATE READ DATA LATENCY IN A MEMORY SYSTEM 审中-公开
标题翻译：用于在存储器系统中提供读取数据延迟的方法和系统
公开(公告)号：US20070183331A1
公开(公告)日：2007-08-09
申请号：US11736196
申请日：2007-04-17
申请人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
发明人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
IPC分类号： H04J1/16
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.
摘要翻译：一种用于在存储器系统中提供不确定的读取数据等待时间的方法和系统。该方法包括确定是否已经接收到本地数据分组。如果接收到本地数据分组，则本地数据分组被存储到缓冲设备中。该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上行驱动器空闲。如果缓冲区包含数据包，并且上游驱动程序处于空闲状态，则将数据包传送到上游驱动程序。该方法还包括确定是否已经接收到上游数据分组。上行数据包是帧格式，包括帧开始指示符和存储器控制器在将上行数据包与其对应的读取指令相关联时使用的识别标签。如果已经接收到上游数据分组，并且上游驱动程序不空闲，则上游数据分组被存储到缓冲设备中。如果已经接收到上游数据分组，并且缓冲设备不包含数据分组，并且上游驱动器空闲，则将上游数据分组发送到上游驱动程序。如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

7. 发明申请

US20070286078A1 METHOD AND SYSTEM FOR PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY 有权
标题翻译：用于在具有INDETERMINATE的存储器系统中提供帧起始指示的方法和系统读取数据延迟
公开(公告)号：US20070286078A1
公开(公告)日：2007-12-13
申请号：US11843150
申请日：2007-08-22
申请人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
发明人： Paul Coteus , Kevin Gower , Warren Maule , Robert Tremaine
IPC分类号： H04J1/16
CPC分类号： G06F13/1657 , G06F13/1673
摘要： A method and system for providing frame start indication in a memory system having indeterminate read data latency. The method includes receiving a data transfer and determining if the data transfer includes a frame start indicator. The method also includes capturing the data transfer and “n” subsequent data transfers in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers comprise a data frame.
摘要翻译：一种用于在具有不确定的读数据延迟的存储器系统中提供帧起始指示的方法和系统。该方法包括接收数据传输并确定数据传输是否包括帧起始指示符。响应于确定数据传输包括帧起始指示符，该方法还包括捕获数据传输和“n”次后续数据传输。数据传输和“n”个后续数据传输包括数据帧。

8. 发明申请

US20070226428A1 Computer compressed memory system and method for storing and retrieving data in a processing system 失效
标题翻译：计算机压缩存储器系统和用于在处理系统中存储和检索数据的方法
公开(公告)号：US20070226428A1
公开(公告)日：2007-09-27
申请号：US11369987
申请日：2006-03-08
申请人： Robert Tremaine , Peter Franaszek
发明人： Robert Tremaine , Peter Franaszek
IPC分类号： G06F13/00
CPC分类号： G06F13/16 , G06F12/0802 , G06F12/10
摘要： A computer compressed memory system for storing and retrieving data in a processing system, includes a memory including at least one memory device for storing at least one of uncompressed data and compressed data, a compressor for encoding data blocks into smaller compressed data blocks for storage in the memory, a decompressor for reconstituting encoded data into original uncompressed data blocks, a memory controller for generating, receiving and responding to memory access requests from processing and input/output units and responsively controlling access to the memory from the compressor and the decompressor for storing and retrieving data, and a hardware priority filter associated with the memory controller for selecting specific memory access requests according to attributes and access type within prescribed rates and under specific conditions.
摘要翻译：一种用于在处理系统中存储和检索数据的计算机压缩存储器系统，包括存储器，其包括用于存储未压缩数据和压缩数据中的至少一个的至少一个存储器设备，用于将数据块编码为较小压缩数据块以用于存储的压缩器存储器，用于将编码数据重构成原始未压缩数据块的解压缩器，存储器控制器，用于生成，接收和响应来自处理和输入/输出单元的存储器访问请求，以及响应地控制来自压缩器和解压缩器的存储器的存取以及检索数据，以及与所述存储器控制器相关联的硬件优先级过滤器，用于根据规定速率内的特定条件下的属性和访问类型来选择特定存储器访问请求。

9. 发明申请

US20070088915A1 Method and apparatus for software-assisted data cache and prefetch control 有权
标题翻译：用于软件辅助数据缓存和预取控制的方法和装置
公开(公告)号：US20070088915A1
公开(公告)日：2007-04-19
申请号：US11250054
申请日：2005-10-13
申请人： Roch Archambault , Yaoqing Gao , Francis O' Connell , Robert Tremaine , Michael Wazlowski , Steven White , Lixin Zhang
发明人： Roch Archambault , Yaoqing Gao , Francis O' Connell , Robert Tremaine , Michael Wazlowski , Steven White , Lixin Zhang
IPC分类号： G06F13/00
CPC分类号： G06F9/3879 , G06F8/4442 , G06F9/30047 , G06F9/3455 , G06F12/0862 , G06F2212/6028
摘要： The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.
摘要翻译：本发明提供了一种用于编译用于管理高速缓存系统的指令的计算机实现的方法，装置和计算机可用程序代码。分析循环结构以识别指令中的缓存和预取条件的数据使用特征以形成识别的预取条件。基于数据使用特性和识别的预取条件将一组控制指令插入到指令中以形成多个修改的指令。编译多组修改指令的集合以生成用于执行的代码以形成编译指令。编译指令中的一组控制指令形成高速缓存管理策略以在执行编译指令期间控制存储器系统中数据的移动。

10. 发明申请

US20060155963A1 Assist thread for injecting cache memory in a microprocessor 有权
公开(公告)号：US20060155963A1
公开(公告)日：2006-07-13
申请号：US11034546
申请日：2005-01-13
申请人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
发明人： Patrick Bohrer , Orran Krieger , Ramakrishnan Rajamony , Michael Rosenfield , Hazim Shafi , Balaram Sinharoy , Robert Tremaine
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3851 , G06F9/4881 , G06F12/0862
摘要： A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式