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1. 发明授权

US5721864A Prefetching instructions between caches 失效
标题翻译：在缓存之间预取指令
公开(公告)号：US5721864A
公开(公告)日：1998-02-24
申请号：US531948
申请日：1995-09-18
申请人： Kevin Arthur Chiarot , Michael John Mayfield , Era Kasturia Nangia , Milford John Peterson
发明人： Kevin Arthur Chiarot , Michael John Mayfield , Era Kasturia Nangia , Milford John Peterson
IPC分类号： G06F9/38 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3814 , G06F12/0862 , G06F9/3802 , G06F9/383
摘要： A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ("inevitable-speculative") and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.
摘要翻译：一种用于在线路M执行期间，从L2高速缓存或主存储器中选择性地将线路M + 1预取入L1指令高速缓存。如果在线路M中存在未解决的分支，则线路M + 1是推测性的并且可以是预先仅从L2缓存中提取到L1指令缓存，而不是从主内存中。在从主存储器中预取行M + 1之前，解决未决行M中的未解析分支。如果没有未解决的分支存在，则线M被承诺（“不可避免的推测”），并且从主内存中预取。以这种方式，不会执行潜在的浪费的预取，并且保留主存储器带宽。

2. 发明授权

US5860150A Instruction pre-fetching of a cache line within a processor 失效
标题翻译：指令预处理器内的高速缓存行
公开(公告)号：US5860150A
公开(公告)日：1999-01-12
申请号：US540374
申请日：1995-10-06
申请人： Kevin Arthur Chiarot , Michael John Mayfield , Era Kasturia Nangia , Milford John Peterson
发明人： Kevin Arthur Chiarot , Michael John Mayfield , Era Kasturia Nangia , Milford John Peterson
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3802 , G06F12/0862
摘要： An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.
摘要翻译：一种用于将数据从主存储器读取到处理器的主高速缓冲存储器中的装置。指令提取请求由处理器产生，并根据提取请求的预测精度分配优先级。比较不同提取请求的优先级，首先为最高优先级提取请求提供服务。如果地址N + 1上的主缓存存储器中存在高速缓存未命中，则指令高速缓存行地址N + 1被预取。

3. 发明授权

US06792524B1 System and method cancelling a speculative branch 失效
标题翻译：系统和方法取消推测分支
公开(公告)号：US06792524B1
公开(公告)日：2004-09-14
申请号：US09137653
申请日：1998-08-20
申请人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
发明人： Milford John Peterson , David Andrew Schroter , Albert James Van Norstrand
IPC分类号： G06F944
CPC分类号： G06F9/3842 , G06F9/3844
摘要： For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.
摘要翻译：对于处理器内的每个预测分支，条目保持在分支历史表中。分支历史表中的条目还包括针对该特定分支指令的过去记录的指示，其指示分支预测在过去如何正确。当与预测分支相关联的字段值超过某个阈值时，指示与该分支指令相关联的过去预测已经处于不可接受的水平，则针对该特定分支指令暂停推测分支指令分派。当先前错误分支预测的频率增加超过预选阈值时，替代实施例利用全局指示符来暂停或取消指令分派。

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