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1. 发明授权

US06181161B2 Apparatus and method for verifying macrocell base field programmable logic devices 有权
标题翻译：宏单元基站可编程逻辑器件的验证装置和方法
公开(公告)号：US06181161B2
公开(公告)日：2001-01-30
申请号：US09340331
申请日：1999-06-28
申请人： Krishna Rangasayee , Brad Ishihara , Kunio Nishiwaki
发明人： Krishna Rangasayee , Brad Ishihara , Kunio Nishiwaki
IPC分类号： G06F738
CPC分类号： G01R31/318519
摘要： A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable address that accepts a sequence of instructions. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verification operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester Array and a margin high operation is performed with a Level Tester Array. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register. Advantageously, relatively large groups of data are loaded into the flip-flops in the ADSR to improve processing.
摘要翻译：在现场可编程逻辑器件中编程和验证基于宏观尺度的架构的方法包括选择触发器的步骤。触发器包含一个接受一系列指令的可编程地址。然后，开关控制器可选择地启用两组开关中的任一个。如果选择了第一组开关，则选择编程操作。如果第二组开关被使能，则选择验证操作。验证操作包括通过一组递增地址自动递增基地址的步骤。对于由递增步骤产生的每个递增地址，使用级别测试器阵列执行余量低操作，并且使用级别测试器阵列执行余量高操作。因此，与现有技术不同，在不使用宏单元扫描寄存器的情况下执行本发明的余量操作。有利地，相对较大的数据组被加载到ADSR中的触发器中以改善处理。

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