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1. 发明授权

US4633396A Automatic complex registration in a electronic cash register 失效
标题翻译：在电子收款机中自动复制注册
公开(公告)号：US4633396A
公开(公告)日：1986-12-30
申请号：US613213
申请日：1984-05-23
申请人： Kensaku Komai , Eiji Yoshida
发明人： Kensaku Komai , Eiji Yoshida
IPC分类号： G07G1/12 , G06F15/02 , G06F13/06
CPC分类号： G07G1/12 , G06Q20/201
摘要： An electronic cash register includes department keys for instructing a department registration operation. A department memory includes a memory area for storing an automatic complex registration number which defines an automatic complex registration operation when a corresponding department key is actuated. A complex registration memory stores a set of desired PLU code numbers related to the automatic complex registration number. Thus, when a desired department key is actuated, the registration related to a plurality of commodities defined by the set of PLU code numbers stored in the complex registration memory is automatically conducted.
摘要翻译：电子收款机包括指示部门注册操作的部门密钥。部门存储器包括用于存储自动复合登记号码的存储区域，当对应的部门密钥被启动时，其定义自动复杂登记操作。复杂的注册存储器存储与自动复杂注册号相关的一组期望的PLU码号。因此，当所需的部门密钥被启动时，自动进行与存储在复杂注册存储器中的由PLU代码集合定义的多个商品相关的注册。

2. 发明授权

US09029789B2 Method for detecting radiation, device thereof, and positron emission tomography scanner 有权
标题翻译：辐射检测方法及其装置及正电子发射断层扫描仪
公开(公告)号：US09029789B2
公开(公告)日：2015-05-12
申请号：US12919358
申请日：2008-04-09
申请人： Kengo Shibuya , Taiga Yamaya , Naoko Inadama , Fumihiko Nishikido , Eiji Yoshida , Hideo Murayama
发明人： Kengo Shibuya , Taiga Yamaya , Naoko Inadama , Fumihiko Nishikido , Eiji Yoshida , Hideo Murayama
IPC分类号： G01T1/202 , G01T1/29
CPC分类号： G01T1/2985 , A61B6/037
摘要： A light receiver for detecting incident time is installed on the side of a radiation source of a scintillator (including a Cherenkov radiation emitter), and information (energy, incident time, an incident position, etc.) on radiation made incident into the scintillator is obtained by the output of the light receiver. It is, thereby, possible to identify an incident position and others of radiation into the scintillator at high accuracy.
摘要翻译：用于检测入射时间的光接收器安装在闪烁体（包括切伦科夫辐射发射器）的辐射源的一侧，并且入射到闪烁体中的辐射的信息（能量，入射时间，入射位置等）是通过光接收器的输出获得。因此，可以以高精度将入射位置和其他辐射识别到闪烁体中。

3. 发明授权

US08709898B2 Fabrication method of semiconductor device and fabrication method of dynamic threshold transistor 有权
标题翻译：半导体器件的制造方法和动态阈值晶体管的制造方法
公开(公告)号：US08709898B2
公开(公告)日：2014-04-29
申请号：US13552274
申请日：2012-07-18
申请人： Masahiro Fukuda , Eiji Yoshida , Yosuke Shimamune
发明人： Masahiro Fukuda , Eiji Yoshida , Yosuke Shimamune
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/12 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1207 , H01L29/0653 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/783 , H01L29/7848
摘要： A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
摘要翻译：一种方法包括：除硅衬底部分之外，蚀刻硅衬底，在其上形成沟道区以在硅衬底部分的第一侧和第二侧分别形成第一和第二沟槽; 通过外延生长具有对硅蚀刻选择性的半导体层和另外的硅层来填充第一和第二沟槽; 通过选择性蚀刻工艺去除半导体层选择性，以在衬底部分的第一侧和第二侧分别在硅层下形成空隙; 至少部分地用掩埋绝缘膜掩埋空隙; 在所述硅衬底部分上形成栅极绝缘膜和栅电极; 以及在所述硅衬底部分的第一侧的所述硅层中形成源极区域以及在所述硅衬底部分的第二侧处形成漏极区域。

4. 发明申请

US20130028595A1 FREQUENCY OFFSET ESTIMATING METHOD AND FREQUENCY OFFSET ESTIMATING APPARATUS 有权
标题翻译：频率偏移估计方法和频率偏移估计装置
公开(公告)号：US20130028595A1
公开(公告)日：2013-01-31
申请号：US13640114
申请日：2011-04-14
申请人： Tadao Nakagawa , Yasushi Takatori , Riichi Kudo , Munehiro Matsui , Koichi Ishihara , Takayuki Kobayashi , Etsushi Yamazaki , Akihide Sano , Eiji Yoshida , Masato Mizoguchi , Yutaka Miyamoto
发明人： Tadao Nakagawa , Yasushi Takatori , Riichi Kudo , Munehiro Matsui , Koichi Ishihara , Takayuki Kobayashi , Etsushi Yamazaki , Akihide Sano , Eiji Yoshida , Masato Mizoguchi , Yutaka Miyamoto
IPC分类号： H04B10/08
CPC分类号： H04L27/2657 , H04L27/2676 , H04L27/2684
摘要： When a circuit that calculates a frequency offset using a shape of a frequency spectrum is implemented by hardware, the circuit size can be reduced. A frequency offset estimating method for estimating the difference between a carrier frequency of a reception signal and the frequency of an output signal of a local oscillator includes performing a discrete Fourier transform on a reception signal previously sampled at a predetermined sampling frequency and outputting a frequency spectrum with a plurality of frequency components, calculating an average power of the frequency spectrum, calculating a threshold by adding a predetermined value to the average power or power obtained by multiplying the average power by a constant, performing 1-bit quantization on powers of the frequency components of the frequency spectrum based on the threshold, and calculating a centroid frequency by multiplying frequencies of the frequency components by powers of 1-bit quantized frequency components, calculating the sum of multiplied products, and dividing the sum of the products by the sum of the powers of the 1-bit quantized frequency components of the frequency spectrum.
摘要翻译：当使用频谱的形状计算频率偏移的电路由硬件实现时，可以减小电路尺寸。用于估计接收信号的载波频率与本地振荡器的输出信号的频率之间的差异的频率偏移估计方法包括对以预定采样频率预先采样的接收信号执行离散付里叶变换，并输出频谱具有多个频率分量，计算频谱的平均功率，通过将平均功率或平均功率乘以常数获得的功率相加预定值来计算阈值，对频率的功率执行1比特量化基于阈值的频谱的分量，并且通过将频率分量的频率乘以1比特量化频率分量的幂来计算质心频率，计算乘积的总和，并将乘积的和除以 1位量化频率分量的功率频谱。

5. 发明申请

US20130009064A1 COINCIDENCE DETERMINATION METHOD AND APPARATUS OF PET DEVICE 审中-公开
标题翻译： PET装置的确定方法和装置
公开(公告)号：US20130009064A1
公开(公告)日：2013-01-10
申请号：US13635753
申请日：2010-03-25
申请人： Eiji Yoshida , Taiga Yamaya
发明人： Eiji Yoshida , Taiga Yamaya
IPC分类号： G01T1/164
CPC分类号： G01T1/2985
摘要： In a coincidence determination processing of a PET device for regarding and counting a pair of annihilation radiations detected within a predetermined time as occurring from the same nuclide, a priority of a line of response to acquire is set and a true coincidence is extracted from multiple coincidences by using information on a detection time difference if a plurality of coincidences are detected with the predetermined time. Consequently, a true coincidence is extracted from multiple coincidences which have heretofore been discarded. This improves detection sensitivity at high radioactive concentration and contributes to an improved dynamic range.
摘要翻译：在从同一个核素发生的在预定时间内检测到的一对湮灭辐射的关联和计数的PET装置的重合确定处理中，设置对获取的响应行的优先级，并且从多个重合中提取真正的重合如果在预定时间内检测到多个重合，则通过使用关于检测时间差的信息。因此，从以前被丢弃的多个巧合中提取出真正的符合性。这提高了在高放射性浓度下的检测灵敏度，并有助于改善动态范围。

6. 发明申请

US20120193717A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120193717A1
公开(公告)日：2012-08-02
申请号：US13310298
申请日：2011-12-02
申请人： Akira KATAKAMI , Eiji Yoshida
发明人： Akira KATAKAMI , Eiji Yoshida
IPC分类号： H01L29/786 , H01L21/762 , H01L21/336
CPC分类号： H01L21/3081 , H01L21/743 , H01L21/76229 , H01L29/665 , H01L29/7833
摘要： A semiconductor device includes a first device isolation insulating film formed in a semiconductor substrate, a first well having a first conductivity type, defined by the first device isolation insulating film, and shallower than the first device isolation insulating film, a second device isolation insulating film formed in the first well, shallower than the first well, and defining a first part of the first well and a second part of the first well, a gate insulating film formed above the first part, a gate electrode formed above the gate insulating film, and an interconnection electrically connected to the second part of the first well and the gate electrode, wherein an electric resistance of the first well in a first region below the second device isolation insulating film is lower than an electric resistance of the first well in a second region other than the first region on the same depth level.
摘要翻译：半导体器件包括形成在半导体衬底中的第一器件隔离绝缘膜，由第一器件隔离绝缘膜限定并且比第一器件隔离绝缘膜浅的具有第一导电类型的第一阱，第二器件隔离绝缘膜形成在第一阱中，比第一阱浅，并且限定第一阱的第一部分和第一阱的第二部分，形成在第一部分上方的栅极绝缘膜，形成在栅极绝缘膜上方的栅电极，以及电连接到第一阱和栅电极的第二部分的互连，其中在第二器件隔离绝缘膜下方的第一区域中的第一阱的电阻低于第二阱中的第一阱的电阻区域以外的第一区域在相同的深度级别。

7. 发明申请

US20120155865A1 OPTICAL SIGNAL TRANSMITTER, AND BIAS VOLTAGE CONTROL METHOD 有权
公开(公告)号：US20120155865A1
公开(公告)日：2012-06-21
申请号：US13393101
申请日：2010-09-07
申请人： Hiroto Kawakami , Eiji Yoshida , Masahiro Tachibana
发明人： Hiroto Kawakami , Eiji Yoshida , Masahiro Tachibana
IPC分类号： H04J14/00
CPC分类号： G02F1/0123 , H04B10/5053 , H04B10/5057 , H04B10/50572 , H04B10/50575 , H04B10/5561
摘要： An optical signal transmitter of the present invention includes: two phase modulating portions; a phase shifter which displaces carrier phases of two output lights from the phase modulating portions by π/2; a multiplexing portion which multiplexes two signal lights, carrier phases of the two signal lights being made orthogonal to each other by the phase shifter; a drive signal electrode portion which supplies a differential data signal to each of four paths of interference optical waveguides, each of the two phase modulating portions having the interference optical waveguides, the differential data signal having an amplitude which is equal to a half-wave voltage Vπ of the two phase modulating portions; a drive amplifier which amplifies the differential data signal to be supplied to each of the four paths of the interference optical waveguides; a data bias electrode portion which supplies a total of four data bias voltages to two arms, each of the two phase modulating portions having the two arms; an orthogonal bias electrode portion which supplies an orthogonal bias voltage to the phase shifter; a data bias power supply portion that adjusts delay times in the two phase modulating portions by applying the data bias voltages to the data bias electrode portion; an orthogonal bias power supply portion that adjusts a delay amount relative to a light output from at least one of the two phase modulating portions by applying the orthogonal bias voltage to the orthogonal bias electrode portion; a dither signal adding portion that adds a dither signal to at most three of the four data bias voltages; a dither detecting portion which detects a wave that is n-times a dither component from an output of the multiplexing portion (where n is an integer equal to or greater than one); and an orthogonal bias control portion which feeds back a detection result of the dither detecting portion to the orthogonal bias power supply portion. The orthogonal bias power supply portion adjusts the delay amount relative to the light output from at least one of the two phase modulating portions by controlling the orthogonal bias voltage to be applied to the orthogonal bias electrode portion based on feedback from the orthogonal bias control portion.

8. 发明申请

US20120119267A1 SEMICONDUCTOR DEVICE PRODUCTION METHOD AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件生产方法和半导体器件
公开(公告)号：US20120119267A1
公开(公告)日：2012-05-17
申请号：US13198773
申请日：2011-08-05
申请人： Eiji Yoshida
发明人： Eiji Yoshida
IPC分类号： H01L29/78 , H01L21/22
CPC分类号： H01L29/1033 , H01L29/4238 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/783
摘要： A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.
摘要翻译：半导体器件制造方法包括：形成包括第一区域的半导体区域，与第一区域连接并且具有比第一区域的宽度小的第二区域，以及与第二区域连接并且具有较小的宽度的第三区域比第二个地区; 形成包括与所述第三区域交叉的第一部分的栅电极和从所述第一部分延伸穿过所述第一区域的第二部分; 在所述栅电极上形成侧壁绝缘膜以覆盖所述第二区域的一部分，同时暴露所述第二区域的剩余部分; 将第二导电型杂质注入第一区域和第二区域的剩余部分; 进行热处理; 去除所述侧壁绝缘膜的一部分，并且在所述第一区域和所述第二区域的剩余部分上形成硅化物层。

9. 发明申请

US20120032272A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR 有权
标题翻译：半导体器件，半导体集成电路，SRAM和用于生产D-MOS晶体管的方法
公开(公告)号：US20120032272A1
公开(公告)日：2012-02-09
申请号：US13118918
申请日：2011-05-31
申请人： Eiji Yoshida , Akihisa Yamaguchi
发明人： Eiji Yoshida , Akihisa Yamaguchi
IPC分类号： H01L27/092 , H01L29/772
CPC分类号： H01L27/092 , H01L21/823475 , H01L21/823493 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/7833
摘要： A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well.
摘要翻译：半导体器件包括硅衬底; 元件隔离区; 包括第一井的元件区域; 接触区域从元件区域延伸到元件区域和接触区域之间的元件隔离区域的子区域的栅电极; 源扩散区; 漏极扩散区域; 与源极扩散区域的下端接触的第一绝缘区域; 接触所述漏极扩散区域的下端的第二绝缘区域; 以及通孔，被配置为将所述栅极电极与所述接触区域电连接。第一阱设置在栅电极下方，并且在子区域下经由硅衬底与接触区域电连接。除了子区域之外的元件隔离区域的下端位于比第一阱的下端低的位置。

10. 发明授权

US07671417B2 Memory cell array, method of producing the same, and semiconductor memory device using the same 有权
标题翻译：存储单元阵列，其制造方法以及使用其的半导体存储器件
公开(公告)号：US07671417B2
公开(公告)日：2010-03-02
申请号：US11840559
申请日：2007-08-17
申请人： Eiji Yoshida , Tetsu Tanaka , Toshihiko Miyashita
发明人： Eiji Yoshida , Tetsu Tanaka , Toshihiko Miyashita
IPC分类号： H01L29/72
CPC分类号： H01L21/845 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L27/1211 , H01L29/66795 , H01L29/6681 , H01L29/7841 , H01L29/785
摘要： A memory cell array includes isolated semiconductor regions formed on a supporting insulating substrate, memory cells formed in the respective semiconductor regions, and insulating regions formed so as to insulate the memory cells. Each memory cell formed in a semiconductor region includes a source region, a drain region, a front gate region formed on a gate insulating film formed on one of side surfaces of the semiconductor region such that the source region and the drain region are separated from each other by the front gate region, and a back gate region formed on a gate insulating film formed on an opposite side surface of the semiconductor region such that the source region and the drain region are separated from each other by the back gate region. Each memory cell shares the back gate region with a memory cell adjacent in a row direction.
摘要翻译：存储单元阵列包括形成在支撑绝缘基板上的隔离半导体区域，形成在各个半导体区域中的存储单元，以及形成为使得存储单元绝缘的绝缘区域。形成在半导体区域中的每个存储单元包括源极区域，漏极区域，形成在形成在半导体区域的一个侧表面上的栅极绝缘膜上的前栅极区域，使得源极区域和漏极区域与每个以及形成在栅极绝缘膜上的背栅极区域，该栅极绝缘膜形成在半导体区域的相对侧表面上，使得源极区域和漏极区域由背栅极区域彼此分离。每个存储单元与在行方向上相邻的存储单元共享背栅区。

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