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    • 2. 发明授权
    • Thermal memory cell and thermal system evaluation
    • 热记忆电池和热系统评估
    • US5159564A
    • 1992-10-27
    • US709718
    • 1991-06-03
    • Kenneth R. SwartzelSudalaimuthu G. GanesanRichard T. KuehnRaymond W. HamakerFarid Sadeghi
    • Kenneth R. SwartzelSudalaimuthu G. GanesanRichard T. KuehnRaymond W. HamakerFarid Sadeghi
    • G01K3/04
    • G01K3/04
    • A method for determining the thermal history of an object is disclosed. The object carries at least two thermal calibration materials having different activation energies. The method comprises: first, exposing an object to a thermal treatment; second, detecting the change in each of the calibration materials caused by the thermal treatment; and third, determining the thermal history of the thermal treatment from the detected changes.Also disclosed are thermal history recording devices comprising one or more metal insulator semiconductor (MIS) capacitors. The insulating layer is non-uniformly doped with mobile charged carriers. Two or more MIS capacitors, each having different activation energies, may be mounted in a common support structure to provide a thermal memory cell. The thermal cells may be used in conjunction with an apparatus for determining the thermal history of the cells as also dislcosed herein.
    • 公开了一种用于确定物体的热历史的方法。 该物体携带至少两种具有不同活化能的热校准材料。 该方法包括:首先将物体暴露于热处理; 第二,检测由热处理引起的每个校准材料的变化; 第三,根据检测到的变化确定热处理的热历史。 还公开了包括一个或多个金属绝缘体半导体(MIS)电容器的热历史记录装置。 绝缘层不均匀地掺杂有移动带电载体。 每个具有不同激活能量的两个或更多个MIS电容器可以安装在公共支撑结构中以提供热存储单元。 热单元可以与用于确定细胞的热历史的装置结合使用,这也是本文中所述的。
    • 4. 发明授权
    • Fabrication method for vertical PNP structure with Schottky barrier
diode emitter utilizing ion implantation
    • 使用离子注入的肖特基势垒二极管发射体垂直PNP结构的制作方法
    • US4412376A
    • 1983-11-01
    • US355059
    • 1982-03-05
    • David E. De BarRaymond W. HamakerGeoffrey B. Stephens
    • David E. De BarRaymond W. HamakerGeoffrey B. Stephens
    • H01L21/265H01L21/8222H01L27/082H01L29/47H01L29/73H01L21/283
    • H01L21/26513H01L21/8222H01L27/0826H01L29/47H01L29/7308
    • A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical PNP. The PNP emitter is formed with a Schottky contact such that only the PNP base region is contained in the NPN emitter junction structure. The structure uses a separately masked ion/implant for the NPN intrinsic base implant which also forms the PNP collector region so that the PNP base doping profile can intercept the PNP collector profile at a lower concentration resulting in lower collector/base capacitance, lower series collector resistance and higher collector/base breakdown voltage for the PNP. Since the base doping concentration is lower in the structure and the emitter has no sidewall capacitance, the PNP emitter-base capacitance is greatly reduced. These features result in an improved frequency response for the PNP structure.
    • 公开了具有肖特基势垒二极管发射极的垂直PNP双极晶体管结构,其简化了在NPN集成电路中组合互补PNP的结构和工艺步骤,并提高了垂直PNP的速度和密度。 PNP发射极由肖特基接触形成,使得只有PNP基极区域包含在NPN发射极结结构中。 该结构使用单独掩蔽的离子/注入用于NPN本征基极注入,其也形成PNP集电极区域,使得PNP基极掺杂分布可以以较低的浓度截取PNP集电极分布,导致较低的集电极/基极电容,下部集电极 电阻和更高的集电极/基极击穿电压。 由于基极掺杂浓度在结构中较低,并且发射极没有侧壁电容,因此PNP发射极 - 基极电容大大降低。 这些特征导致PNP结构的频率响应得到改善。