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1. 发明授权

US06344129B1 Method for plating copper conductors and devices formed 有权
标题翻译：电镀铜导体和器件的方法
公开(公告)号：US06344129B1
公开(公告)日：2002-02-05
申请号：US09418197
申请日：1999-10-13
申请人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
发明人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
IPC分类号： C25D500
CPC分类号： C25D5/10 , C25D3/38 , C25D5/00 , C25D7/123 , C25D21/02 , H05K3/423
摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.
摘要翻译：公开了一种在电子基板上镀铜导体的方法和形成的器件。在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

2. 发明授权

US06979393B2 Method for plating copper conductors and devices formed 失效
标题翻译：电镀铜导体和器件的方法
公开(公告)号：US06979393B2
公开(公告)日：2005-12-27
申请号：US10055134
申请日：2002-01-22
申请人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
发明人： Kenneth P. Rodbell , Panayotis C. Andricacos , Cyril Cabral, Jr. , Lynne M. Gignac , Cyprian E. Uzoh , Peter S. Locke
IPC分类号： C25D3/38 , C25D5/00 , C25D5/10 , C25D7/12 , H05K3/42 , C25D5/02
CPC分类号： C25D5/10 , C25D3/38 , C25D5/00 , C25D7/123 , C25D21/02 , H05K3/423
摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.
摘要翻译：公开了一种在电子基板上镀铜导体的方法和形成的器件。在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如具有大于1/3或高达1的直径/深度的纵横比的双镶嵌结构中的通孔 / 10。各种电镀参数用于在单步沉积或双步沉积过程中提供短电阻瞬变。这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。

3. 发明授权

US06331237B1 Method of improving contact reliability for electroplating 失效
标题翻译：提高电镀接触可靠性的方法
公开(公告)号：US06331237B1
公开(公告)日：2001-12-18
申请号：US09387856
申请日：1999-09-01
申请人： Panayotis C. Andricacos , W. Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Cyprian E. Uzoh
发明人： Panayotis C. Andricacos , W. Jean Horkans , Keith T. Kwietniak , Peter S. Locke , Cyprian E. Uzoh
IPC分类号： C25D2106
CPC分类号： C25D7/123 , C25D5/003 , C25D21/12 , C25D21/18
摘要： A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
摘要翻译：通过电镀液减少种子层的蚀刻的方法。在将具有种子层的半导体晶片引入电镀液之前，电镀液的蚀刻功率降低。

4. 发明授权

US06251251B1 Anode design for semiconductor deposition 失效
标题翻译：用于半导体沉积的阳极设计
公开(公告)号：US06251251B1
公开(公告)日：2001-06-26
申请号：US09192431
申请日：1998-11-16
申请人： Cyprian E. Uzoh , Panayotis C. Andricacos , John Owen Dukovic , Robert P. Westerfield, Jr.
发明人： Cyprian E. Uzoh , Panayotis C. Andricacos , John Owen Dukovic , Robert P. Westerfield, Jr.
IPC分类号： C25D2118
CPC分类号： C25D7/12 , C25D17/001 , C25D17/12
摘要： An anode assembly including a perforated anode. A perforated anode holder holds the anode. The anode holder includes perforations at least in a bottom wall such that plating solution may flow through perforations in the anode holder and perforations in the anode. An anode isolator separates the anode and a cathode. The anode isolator includes at least one curvilinear surface.
摘要翻译：包括穿孔阳极的阳极组件。穿孔阳极支架固定阳极。阳极保持器至少在底壁中具有穿孔，使得电镀溶液可以流过阳极保持器中的穿孔和阳极中的穿孔。阳极隔离器分离阳极和阴极。阳极隔离器包括至少一个曲线表面。

5. 发明授权

US06600230B2 Seedlayer for plating metal in deep submicron structures 失效
标题翻译：用于在深亚微米结构中电镀金属的种子层
公开(公告)号：US06600230B2
公开(公告)日：2003-07-29
申请号：US09899923
申请日：2001-07-09
申请人： Cyprian E. Uzoh , Peter S. Locke
发明人： Cyprian E. Uzoh , Peter S. Locke
IPC分类号： H01L2348
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76877 , Y10T428/12 , Y10T428/12528 , Y10T428/239 , Y10T428/24917
摘要： A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.
摘要翻译：在亚微米结构中电镀金属的方法。种子层沉积在亚微米结构的表面上。种子层在约80℃至约130℃的温度下退火。将金属镀在种子层上。

6. 发明授权

US06258717B1 Method to produce high quality metal fill in deep submicron vias and lines 失效
公开(公告)号：US06258717B1
公开(公告)日：2001-07-10
申请号：US09363741
申请日：1999-07-30
申请人： Cyprian E. Uzoh , Peter S. Locke
发明人： Cyprian E. Uzoh , Peter S. Locke
IPC分类号： H01L2144
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76877 , Y10T428/12 , Y10T428/12528 , Y10T428/239 , Y10T428/24917
摘要： A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.

7. 发明授权

US06413854B1 Method to build multi level structure 失效
标题翻译：构建多层结构的方法
公开(公告)号：US06413854B1
公开(公告)日：2002-07-02
申请号：US09382110
申请日：1999-08-24
申请人： Cyprian E. Uzoh , Daniel C. Edelstein , Cheryl Faltermeier , Peter S. Locke
发明人： Cyprian E. Uzoh , Daniel C. Edelstein , Cheryl Faltermeier , Peter S. Locke
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76801 , H01L21/76831 , H01L21/76834 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a structure. A first dielectric material is deposited on a substrate. The first dielectric material is patterned. At least one metal is deposited in and on the first dielectric material. Portions of the at least one metal are removed at least in a region above an upper surface of the first dielectric material. The first dielectric material is removed. A second dielectric material is provided in place of first dielectric material.
摘要翻译：一种形成结构的方法。第一介电材料沉积在基底上。第一介电材料被图案化。至少一种金属沉积在第一介电材料中和之上。至少一个金属的部分至少在第一介电材料的上表面上方的区域中被去除。去除第一介电材料。提供第二电介质材料代替第一电介质材料。

8. 发明授权

US07416975B2 Method of forming contact layers on substrates 有权
标题翻译：在基片上形成接触层的方法
公开(公告)号：US07416975B2
公开(公告)日：2008-08-26
申请号：US11232718
申请日：2005-09-21
申请人： Cyprian E. Uzoh , Bulent M. Basol , Hung-Ming Wang , Homayoun Talieh
发明人： Cyprian E. Uzoh , Bulent M. Basol , Hung-Ming Wang , Homayoun Talieh
IPC分类号： H01L21/44
CPC分类号： H01L21/2885 , C25D5/02 , C25D7/123 , C25D17/005
摘要： A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.
摘要翻译：提供了一种用于在基板的表面上制造可移除接触结构以在电加工期间将电从接触构件传导到表面的方法。该方法包括在表面上形成导电层。导电层的预定区域被接触层选择性地涂覆，使得当在导电层上进行电处理时，接触构件接触接触层。

9. 发明授权

US06861354B2 Method and structure to reduce defects in integrated circuits and substrates 失效
标题翻译：降低集成电路和基板缺陷的方法和结构
公开(公告)号：US06861354B2
公开(公告)日：2005-03-01
申请号：US10358565
申请日：2003-02-04
申请人： Cyprian E. Uzoh , Homayoun Talieh , Bulent M. Basol
发明人： Cyprian E. Uzoh , Homayoun Talieh , Bulent M. Basol
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2885 , H01L21/7684 , H01L21/76864 , H01L21/76873 , H01L21/76877 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method for forming conductor structures on a semiconductor wafer is provided. The method begins with depositing a seed layer having a substantially consistent thickness over a barrier layer that covers the features and the field regions among them. The process continues with electrodepositing a planar copper layer on the seed layer and subsequently electroetching it until a thinned seed layer remains over the field regions. When another layer of planar copper is deposited on the remaining copper in the features and on the thinned seed layer on the field regions, this structure minimizes stress related defects in the features which occur during a following anneal process.
摘要翻译：提供了一种在半导体晶片上形成导体结构的方法。该方法开始于在覆盖其中的特征和场区域的阻挡层上沉积具有基本上一致的厚度的种子层。该过程继续在种子层上电沉积平面铜层，随后电蚀，直到变薄的种子层保留在场区域上。当另一层平面铜沉积在特征中的剩余铜上以及在场区上的薄化种子层上时，该结构使得在随后的退火过程中发生的特征中的应力相关缺陷最小化。

10. 发明授权

US06777338B2 Edge and bevel cleaning process and system 有权
标题翻译：边缘和斜面清洁过程和系统
公开(公告)号：US06777338B2
公开(公告)日：2004-08-17
申请号：US10051755
申请日：2002-01-15
申请人： Jalal Ashjaee , Rimma Volodarsky , Cyprian E. Uzoh , Bulent M. Basol , Homayoun Talieh
发明人： Jalal Ashjaee , Rimma Volodarsky , Cyprian E. Uzoh , Bulent M. Basol , Homayoun Talieh
IPC分类号： H01L21461
CPC分类号： H01L21/6708 , H01L21/2885 , H01L21/32134
摘要： The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof. The at least one nozzle is located in an upper chamber of a vertically configured processing subsystem that also includes mechanisms for plating, cleaning and drying in upper and lower chambers.
摘要翻译：本发明提供了至少一个喷嘴，其在其边缘处用蚀刻剂喷射旋转的工件。至少一个喷嘴位于垂直配置的处理子系统的上部室中，其还包括用于上部和下部室中的电镀，清洁和干燥的机构。

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