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1. 发明授权

US5134310A Current supply circuit for driving high capacitance load in an integrated circuit 失效
标题翻译：用于在集成电路中驱动高电容负载的电流供应电路
公开(公告)号：US5134310A
公开(公告)日：1992-07-28
申请号：US644903
申请日：1991-01-23
申请人： Kenneth J. Mobley , S. Sheffield Eaton, Jr.
发明人： Kenneth J. Mobley , S. Sheffield Eaton, Jr.
IPC分类号： G11C11/409 , G11C7/06 , G11C11/406 , H03F3/343 , H03K17/687
CPC分类号： G11C7/06
摘要： A constant current power supply circuit for an integrated circuit memory which is well suited for driving a high capacitance load, such as a large number of sense amplifiers. A first circuit provides a constant current source and a second "current mirror" circuit provides an output current proportionate to the first circuit, but at a higher desired level of current. The constant current circuit is achieved using two cross-coupled FET transistors and two resistances such that the conductivity of each transistor is inversely related to the conductivity of the other. The circuit reaches a constant current equilibrium which is largely independent of operating voltage or load, but rather depends on the relative values of the components.

2. 发明授权

US5117177A Reference generator for an integrated circuit 失效
标题翻译：用于集成电路的参考发生器
公开(公告)号：US5117177A
公开(公告)日：1992-05-26
申请号：US644904
申请日：1991-01-23
申请人： S. Sheffield Eaton, Jr.
发明人： S. Sheffield Eaton, Jr.
IPC分类号： G05F3/24 , H02M3/07
CPC分类号： H02M3/07 , G05F3/247
摘要： A voltage reference generated for an integrated circuit which produces a source of reference voltage which is self-compensated for variations in operating voltage (V.sub.cc) or in transistor threshold voltages (V.sub.T). The circuit uses a voltage divider coupled between V.sub.cc and ground and has first and second FET transistors. A faced control circuit is coupled to control the conductivity of the first transistor, and the second control circuit is coupled to control the conductivity of the second transistor. The first control circuit produces a control voltage which varies as a function of variations in V.sub.cc, while the second control circuit also provides a control voltage wherein variations are a function of variations in V.sub.cc, but in an opposite direction. Hence, the second control voltage is configured so that variations in V.sub.cc cause the second transistor to compensate for changes in operation of the first transistor, so that the reference voltage remains substantially constant.
摘要翻译：产生用于集成电路的电压基准，其产生对工作电压（Vcc）或晶体管阈值电压（VT）中的变化进行自补偿的参考电压源。该电路使用耦合在Vcc和地之间的分压器，并具有第一和第二FET晶体管。耦合面对的控制电路以控制第一晶体管的导电性，并且第二控制电路被耦合以控制第二晶体管的导电性。第一控制电路产生作为Vcc变化的函数而变化的控制电压，而第二控制电路还提供控制电压，其中变化是Vcc变化但是在相反方向上的变化。因此，第二控制电压被配置为使得Vcc的变化使得第二晶体管补偿第一晶体管的操作变化，使得参考电压基本保持不变。

3. 发明授权

US4570331A Thick oxide field-shield CMOS process 失效
标题翻译：厚氧化物场屏蔽CMOS工艺
公开(公告)号：US4570331A
公开(公告)日：1986-02-18
申请号：US574056
申请日：1984-01-26
申请人： S. Sheffield Eaton, Jr. , Cheng-Cheng Hu
发明人： S. Sheffield Eaton, Jr. , Cheng-Cheng Hu
IPC分类号： H01L27/10 , G11C11/34 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/08 , H01L27/088 , H01L27/105 , H01L27/108 , H01L21/94 , H01L21/265
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/105 , Y10S148/082
摘要： An improved semiconductor structure and the method for fabricating such is disclosed. The invention relates to the use of thick-oxide for improved field-shield isolation especially as applied to dynamic RAMS's and also to its integration into an improved CMOS process. The improved structure has increased isolation characteristics between adjacent memory cells and still allows for lessened spacing between cells. The corresponding process determines the spacing between cells through etching and eliminates several steps by utilizing one mask for several purposes including defining the active transistor areas and the first polysilicon layer and by extending the use of the first polysilicon layer for field-shield isolation between cells. Additional advantages are disclosed including a higher body effect in the isolation transistors, use of a nitride dielectric layer, and a higher, stable threshold voltage in the isolation transistors. Also, modification of the improved process for fabrication of P-channel and N-channel devices can be made.
摘要翻译：公开了一种改进的半导体结构及其制造方法。本发明涉及厚氧化物用于改进的场屏蔽隔离的用途，特别是应用于动态RAMS以及其与改进的CMOS工艺的集成。改进的结构增加了相邻存储单元之间的隔离特性，并且仍允许在单元之间减小间隔。相应的处理通过蚀刻确定单元之间的间隔，并且通过利用一个掩模用于若干目的来消除几个步骤，包括限定有源晶体管区域和第一多晶硅层，并且通过扩展使用第一多晶硅层用于在单元之间进行场屏蔽隔离。公开了另外的优点，其包括在隔离晶体管中具有更高的体效应，使用氮化物电介质层，以及在隔离晶体管中具有较高稳定的阈值电压。此外，可以对P沟道和N沟道器件的制造改进过程进行修改。

4. 发明授权

US5317538A Low power DRAM 失效
标题翻译：低功耗DRAM
公开(公告)号：US5317538A
公开(公告)日：1994-05-31
申请号：US859670
申请日：1992-03-30
申请人： S. Sheffield Eaton, Jr.
发明人： S. Sheffield Eaton, Jr.
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4074 , G11C5/14
CPC分类号： G11C11/4074
摘要： In a DRAM, a logic "1" is redefined as the minimum VCC value minus one threshold voltage. The word line is not bootstrapped. This intermediate voltage is applied via the sense amplifier to the bit lines during refresh. The intermediate value is controlled preferably by a comparator controlling a driver. Even when the power supply voltage rises, the intermediate voltage is held constant by comparison to a fixed reference voltage. Operating current is substantially reduced because less power is required to write data into the memory cells, since a controlled lower voltage is used.
摘要翻译：在DRAM中，逻辑“1”被重新定义为最小VCC值减去一个阈值电压。字线不引导。在刷新期间，该中间电压通过读出放大器施加到位线。中间值优选地由控制驾驶员的比较器控制。即使电源电压上升，与固定的基准电压相比，中间电压也保持恒定。由于使用受控的较低电压，因此需要较少的功率来将数据写入存储单元，所以工作电流大大降低。

5. 发明授权

US5109357A DRAM memory cell and method of operation thereof for transferring increased amount of charge to a bit line 失效
标题翻译： DRAM存储单元及其操作方法，用于将增加的电荷量转移到位线
公开(公告)号：US5109357A
公开(公告)日：1992-04-28
申请号：US491180
申请日：1990-03-09
申请人： S. Sheffield Eaton, Jr.
发明人： S. Sheffield Eaton, Jr.
IPC分类号： G11C11/22 , G11C11/404 , H01L27/108 , H01L27/115 , H01L29/92
CPC分类号： H01L27/11502 , G11C11/22 , G11C11/404 , H01L27/10808 , H01L28/40
摘要： An improved DRAM memory cell uses ferroelectric material as the dielectric between capacitor plates. Preferably polycrystalline PZT or a perovskite is used for the ferroelectric, and the polar axes of the dipoles in the ferroelectric material in relaxed position are not aligned with the direction of the resulting electric field when voltage is applied to the capacitor plates. Preferably, the dipole orientation is in the plane of the ferroelectric film so that when a write voltage is removed from the capacitor plate, the dipoles tend to relax to a non-aligned position. When the cell is read or refreshed, increased charge is drawn from the bit line and resides on the capacitor plate in order to reorient the relaxed dipoles. The charge developed on the plate hence is magnified.
摘要翻译：改进的DRAM存储单元使用铁电材料作为电容器板之间的电介质。优选地，将多晶PZT或钙钛矿用于铁电体，并且当放电位置的铁电材料中的偶极子的极轴在电压施加到电容器板时不与所得电场的方向对准。优选地，偶极取向在铁电膜的平面中，使得当从电容器板去除写入电压时，偶极子趋向于放松到非对准位置。当单元被读取或刷新时，从位线引出增加的电荷并驻留在电容器板上，以便重新定向松弛的偶极子。因此在板上产生的电荷被放大。

6. 发明授权

US4918654A SRAM with programmable capacitance divider 失效
标题翻译：具有可编程电容分压器的SRAM
公开(公告)号：US4918654A
公开(公告)日：1990-04-17
申请号：US292818
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

7. 发明授权

US4910708A Dram with programmable capacitance divider 失效
标题翻译： Dram可编程电容分压器
公开(公告)号：US4910708A
公开(公告)日：1990-03-20
申请号：US292891
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

8. 发明授权

US4809225A Memory cell with volatile and non-volatile portions having ferroelectric capacitors 失效
标题翻译：具有铁电电容器的具有挥发性和非易失性部分的存储单元
公开(公告)号：US4809225A
公开(公告)日：1989-02-28
申请号：US69390
申请日：1987-07-02
申请人： Klaus Dimmler , S. Sheffield Eaton, Jr.
发明人： Klaus Dimmler , S. Sheffield Eaton, Jr.
IPC分类号： G11C11/22 , G11C11/412 , G11C14/00 , H01L21/822 , H01L21/8244 , H01L21/8246 , H01L21/8247 , H01L27/04 , H01L27/105 , H01L27/11 , H01L29/788 , H01L29/792 , G11C11/00 , G11C11/24 , G11C11/34
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A memory cell includes an SRAM flip-flop cell having two nodes coupled to ferroelectric capacitors so that when the SRAM is powered down, the ferroelectric devices store data and upon power up, transfer the stored data to the SRAM cell. The ferroelectric devices can be bypassed during normal SRAM operations to reduce hysteresis fatigue.

9. 发明授权

US5253205A Bit line and cell plate clamp circuit for a DRAM 失效
标题翻译： DRAM的位线和单元板钳位电路
公开(公告)号：US5253205A
公开(公告)日：1993-10-12
申请号：US755111
申请日：1991-09-05
申请人： S. Sheffield Eaton, Jr.
发明人： S. Sheffield Eaton, Jr.
IPC分类号： G11C11/409 , G11C11/401 , G11C11/404 , G11C11/407 , G11C11/4074 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/4094
摘要： A supply circuit providing an intermediate voltage between Vss and Vcc for a DRAM is coupled to both the cell capacitor plates and the bit line clamp transistors. The supply circuit includes a logic circuit which ANDs the equilibration signal and a restore complete signal thereby to provide a timing signal in the initial portion of the precharge epoch. The timing signal turns on first and second transistors which operate as a load to develop a voltage at first and second nodes. The voltage so developed is a transition voltage above the target holding voltage. This voltage is stored on a storage capacitor, and to the gate electrode of a drive transistor and a third transistor. The drive transistor selectively couples operating voltage to the hold line. After the logic circuit turns off, the offset voltage which has been stored on the capacitor controls the drive transistor to couple the target holding voltage to the holding line.

10. 发明授权

US4914627A One transistor memory cell with programmable capacitance divider 失效
标题翻译：一个具有可编程电容分压器的晶体管存储单元
公开(公告)号：US4914627A
公开(公告)日：1990-04-03
申请号：US292776
申请日：1989-01-03
申请人： S. Sheffield Eaton, Jr. , Michael Parris
发明人： S. Sheffield Eaton, Jr. , Michael Parris
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/0072 , G11C11/22 , G11C14/00
摘要： A transpolarizer is employed as a programmable capacitance divider. Two ferroelectric capacitors are coupled in series to form a common node and two extreme poles. The polarization of the two capacitors is set by grounding the two poles and then bringing them both up to VCC while impressing a voltage at the common node corresponding to data to be stored. Therefore, while one pole is held at VSS, the other pole is pulsed from VSS to VCC with the common node floating. A voltage develops at the common node which is above or below the midpoint between VSS and VCC, and will be indicative of the stored data. The capacitance divider is programmed in accordance with data. One such divider is added to a DRAM memory cell to form a shadow DRAM cell. Two such dividers are added to a static RAM memory cell to form a shadow static RAM cell. The same divider arrangement is operable in both volatile and non-volatile modes. An improvement arises by using PZT as dielectric in 54:46 mole ratio.
摘要翻译：偏振器用作可编程电容分压器。两个铁电电容器串联耦合以形成公共节点和两个极端极。两个电容器的极化通过将两极接地而设置，然后将它们两者都设置为VCC，同时在与要存储的数据相对应的公共节点处施加电压。因此，当一个极点保持在VSS时，另一个极点从VSS脉冲到VCC，公共节点浮动。在VSS和VCC之间的中点之上或之下的公共节点处产生电压，并且将指示存储的数据。电容分压器根据数据进行编程。一个这样的分频器被添加到DRAM存储器单元以形成阴影DRAM单元。将两个这样的分频器添加到静态RAM存储器单元中以形成阴影静态RAM单元。相同的分配器布置可在易失性和非易失性模式下操作。通过使用PZT作为54:46摩尔比的电介质来改善。

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