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1. 发明授权

US06816345B1 Magnetoresistive sensors having submicron track widths and method of making 失效
标题翻译：具有亚微米轨道宽度和制造方法的磁阻传感器
公开(公告)号：US06816345B1
公开(公告)日：2004-11-09
申请号：US09963288
申请日：2001-09-24
申请人： Kenneth E. Knapp , Ronald A. Barr , Myron R. Cagan , Mark D. Thomas
发明人： Kenneth E. Knapp , Ronald A. Barr , Myron R. Cagan , Mark D. Thomas
IPC分类号： G11B539
CPC分类号： G11B5/3932
摘要： Methods for reducing feature sizes of devices such as electromagnetic sensors are disclosed. A track width of a MR sensor is defined by a mask having an upper layer with a reduced width and a lower layer with a further reduced width. Instead of or in addition to being supported by the lower layer in the area defining the sensor, the upper layer is supported by the lower layer in areas that do not define the sensor width. In some embodiments the upper layer forms a bridge mask, supported at its ends by the lower layer, and the lower layer is completely removed over an area that will become a sensor. Also disclosed is a mask having more than two layers, with a bottom layer completely removed over the sensor area, and a middle layer undercut relative to a top layer.
摘要翻译：公开了用于减小诸如电磁传感器的装置的特征尺寸的方法。 MR传感器的轨道宽度由具有减小宽度的上层的掩模和具有进一步减小的宽度的下层限定。在限定传感器的区域中由下层支撑或替代地，上层在不限定传感器宽度的区域中由下层支撑。在一些实施例中，上层形成桥接掩模，其端部由下层支撑，并且下层在将成为传感器的区域上被完全移除。还公开了具有多于两层的掩模，其中底层在传感器区域上完全去除，并且相对于顶层底切的中间层。

2. 发明授权

US6040619A Semiconductor device including antireflective etch stop layer 失效
标题翻译：半导体器件包括抗反射蚀刻停止层
公开(公告)号：US6040619A
公开(公告)日：2000-03-21
申请号：US937774
申请日：1997-09-25
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L21/28 , H01L21/027 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/768 , H01L21/8244 , H01L23/522 , H01L27/11 , H01L29/78 , H01L23/58 , H01L21/316 , H01L23/48
CPC分类号： H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量比的高硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

3. 发明授权

US06313018B1 Process for fabricating semiconductor device including antireflective etch stop layer 有权
标题翻译：用于制造包括抗反射蚀刻停止层的半导体器件的工艺
公开(公告)号：US06313018B1
公开(公告)日：2001-11-06
申请号：US09504449
申请日：2000-02-16
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L2120
CPC分类号： H01L21/0214 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量的硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

4. 发明授权

US5045918A Semiconductor device with reduced packaging stress 失效
标题翻译：半导体器件具有降低的封装应力
公开(公告)号：US5045918A
公开(公告)日：1991-09-03
申请号：US504710
申请日：1990-04-04
申请人： Myron R. Cagan , Douglas F. Ridley , Daniel J. Belton
发明人： Myron R. Cagan , Douglas F. Ridley , Daniel J. Belton
IPC分类号： H01L23/31
CPC分类号： H01L24/85 , H01L23/3135 , H01L23/3157 , H01L24/03 , H01L24/05 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/8592 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01043 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/20752 , H01L2924/20753
摘要： A semiconductor device contains a stress-relief layer (46) having a glass transition temperature of 25.degree. C. or less. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer preferably is a silicone polymer consisting of exposed photosensitive material.
摘要翻译：半导体器件包含玻璃化转变温度为25℃以下的应力消除层（46）。该层通常位于设备中的电互连系统（12）的上方，但不覆盖接合焊盘区域。这实质上减轻了可能会损坏器件中的电子部件的热诱导应力，同时允许从外部封装涂层（48）突出的电导体（32和34）上的最大应力发生在可容忍应力的接合区域。该层优选是由暴露的感光材料组成的硅氧烷聚合物。

5. 发明授权

US5171716A Method of manufacturing semiconductor device with reduced packaging stress 失效
标题翻译：制造具有降低的包装应力的半导体器件的方法
公开(公告)号：US5171716A
公开(公告)日：1992-12-15
申请号：US709242
申请日：1991-06-03
申请人： Myron R. Cagan , Douglas F. Ridley , Daniel J. Belton
发明人： Myron R. Cagan , Douglas F. Ridley , Daniel J. Belton
IPC分类号： H01L23/31
CPC分类号： H01L23/3157 , H01L23/3135 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L24/45 , H01L24/48 , H01L2924/01006 , H01L2924/01014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , Y10S148/103
摘要： A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150.degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.
摘要翻译：半导体器件包含玻璃化转变温度低于150℃的应力消除层（46）。该层通常位于器件中的电互连系统（12）的上方，但不覆盖焊盘区域。这实质上减轻了可能会损坏器件中的电子部件的热诱导应力，同时允许从外部封装涂层（48）突出的电导体（32和34）上的最大应力发生在可容忍应力的接合区域。该层优选通过光刻图案制成。

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