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1. 发明授权

US08401195B2 Method of automatically populating a list of managed secure communications group members 有权
标题翻译：自动填充受管理的安全通信组成员列表的方法
公开(公告)号：US08401195B2
公开(公告)日：2013-03-19
申请号：US12234828
申请日：2008-09-22
申请人： Kenneth C. Fuchs , Larry Murrill
发明人： Kenneth C. Fuchs , Larry Murrill
IPC分类号： H04L9/00 , H04L9/08 , H04L29/06 , H04L9/32 , G06F21/00
CPC分类号： H04L9/0833 , H04L63/065 , H04L2209/80 , H04W12/04
摘要： Methods of automatically populating a secure group list in a key variable loader and of providing keys to a secure group are presented. After a user selects a secure group and encryption algorithm using inputs of the loader, the loader provides a group identifier and corresponding key for the group. The group identifier, encryption algorithm, and key are transmitted to a portable communication device over a physical connection between the two while a device identifier of the communication device is transmitted concurrently to the loader. The key variable loader automatically populates a stored list of subscribers of the group with the device identifier. When it is desired to transmit a new key to all of or fewer than all of the subscribers, one of the subscribers is connected with the loader and used to wirelessly transmit a new key to the remaining subscribers.
摘要翻译：呈现在密钥变量加载器中自动填充安全组列表并向安全组提供密钥的方法。在用户使用加载器的输入选择安全组和加密算法之后，加载器为组提供组标识符和相应的密钥。通过两者之间的物理连接将组标识符，加密算法和密钥发送到便携式通信设备，同时将通信设备的设备标识符同时发送到加载器。密钥变量加载器使用设备标识符自动填充存储的用户列表。当希望将新密钥发送到全部或少于所有订户时，其中一个订户与加载器连接，并用于向剩余订户无线传输新密钥。

2. 发明申请

US20110239308A1 SYSTEM AND METHOD OF VETTING DATA 有权
标题翻译：系统和数据的方法
公开(公告)号：US20110239308A1
公开(公告)日：2011-09-29
申请号：US12748645
申请日：2010-03-29
申请人： Kenneth C. Fuchs , Brian W. Pruss , Gary W. Schluckbier
发明人： Kenneth C. Fuchs , Brian W. Pruss , Gary W. Schluckbier
IPC分类号： G06F21/24 , G06F11/16
CPC分类号： G06F9/526
摘要： Systems and methods for vetting data include receiving a notification at a second processor that a first processor has written first output data to an output data buffer in an output device. A hardware-implemented buffer access flag controls a permission for the first processor to write data to the output data buffer. The second processor sets the hardware-implemented buffer access flag to a first setting that prevents the first processor from writing additional output data to the output data buffer while the first output data in the output data buffer is being inspected. The second processor has a read-write permission to the hardware-implemented buffer access flag. The first processor has a read-only permission to the hardware-implemented buffer access flag.
摘要翻译：用于审查数据的系统和方法包括在第二处理器处接收到第一处理器已将第一输出数据写入输出设备中的输出数据缓冲器的通知。硬件实现的缓冲器访问标志控制第一处理器将数据写入输出数据缓冲器的权限。第二处理器将硬件实现的缓冲器访问标志设置为第一设置，以防止在检查输出数据缓冲器中的第一输出数据时第一处理器将额外的输出数据写入输出数据缓冲器。第二个处理器具有对硬件实现的缓冲区访问标志的读写权限。第一个处理器具有对硬件实现的缓冲区访问标志的只读权限。

3. 发明授权

US08250356B2 Method to construct a high-assurance IPSec gateway using an unmodified commercial implementation 有权
标题翻译：使用未经修改的商业实现构建高保证IPSec网关的方法
公开(公告)号：US08250356B2
公开(公告)日：2012-08-21
申请号：US12275322
申请日：2008-11-21
申请人： Brian W. Pruss , Kenneth C. Fuchs , Timothy M. Langham
发明人： Brian W. Pruss , Kenneth C. Fuchs , Timothy M. Langham
IPC分类号： H05L29/06
CPC分类号： H04L63/0485 , H04L63/0263 , H04L63/164
摘要： A system and method of providing secure communications is provided. Messages are encrypted or decrypted in protected memory of a processor. Outbound messages from a secure network are prepared for encryption by adding a header outside of the protected memory and then encrypted in the protected memory. The encryption is performed by retrieving a key from a key cache as designated by rules in the header. The encrypted message is sent to the unsecure network. An inbound message from an unsecure network that is received in unprotected memory is sent to a decryption module in protected memory. The inbound message is decrypted using a key designated in its header and retrieved from the key cache. The decrypted message is returned to the unprotected memory, where it is stripped of the encryption header and then sent to its destination within the secure network.
摘要翻译：提供了提供安全通信的系统和方法。消息在处理器的受保护的存储器中被加密或解密。来自安全网络的出站消息通过在受保护的存储器之外添加头部然后在受保护的存储器中加密来准备加密。通过从标题中的规则指定的密钥缓存中检索密钥来执行加密。加密的消息被发送到不安全的网络。在未受保护的存储器中接收到的来自不安全网络的入站消息被发送到受保护存储器中的解密模块。使用在其报头中指定的并从密钥高速缓存中检索的密钥解密入站消息。解密的消息被返回到不受保护的存储器，其中它被剥离加密头部，然后在安全网络内发送到其目的地。

4. 发明授权

US08424100B2 System and method of vetting data 有权
标题翻译：审查数据的制度和方法
公开(公告)号：US08424100B2
公开(公告)日：2013-04-16
申请号：US12748645
申请日：2010-03-29
申请人： Kenneth C. Fuchs , Brian W. Pruss , Gary W. Schluckbier
发明人： Kenneth C. Fuchs , Brian W. Pruss , Gary W. Schluckbier
IPC分类号： G06F7/04
CPC分类号： G06F9/526
摘要： Systems and methods for vetting data include receiving a notification at a second processor that a first processor has written first output data to an output data buffer in an output device. A hardware-implemented buffer access flag controls a permission for the first processor to write data to the output data buffer. The second processor sets the hardware-implemented buffer access flag to a first setting that prevents the first processor from writing additional output data to the output data buffer while the first output data in the output data buffer is being inspected. The second processor has a read-write permission to the hardware-implemented buffer access flag. The first processor has a read-only permission to the hardware-implemented buffer access flag.
摘要翻译：用于审查数据的系统和方法包括在第二处理器处接收到第一处理器已将第一输出数据写入输出设备中的输出数据缓冲器的通知。硬件实现的缓冲器访问标志控制第一处理器将数据写入输出数据缓冲器的权限。第二处理器将硬件实现的缓冲器访问标志设置为第一设置，以防止在检查输出数据缓冲器中的第一输出数据时第一处理器将额外的输出数据写入输出数据缓冲器。第二个处理器具有对硬件实现的缓冲区访问标志的读写权限。第一个处理器具有对硬件实现的缓冲区访问标志的只读权限。

5. 发明授权

US07406711B2 Method and apparatus for enforcing independence of processors on a single IC 有权
标题翻译：在单个IC上实现处理器独立性的方法和装置
公开(公告)号：US07406711B2
公开(公告)日：2008-07-29
申请号：US11218361
申请日：2005-09-02
申请人： Kenneth C. Fuchs , Brian W. Pruss , Timothy M. Langham
发明人： Kenneth C. Fuchs , Brian W. Pruss , Timothy M. Langham
IPC分类号： G06F21/00
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/0745 , G06F11/0772 , G06F11/1637
摘要： A single-chip integrated circuit comprising a first processor for executing a plurality of applications, a second processor for executing a plurality of applications, at least one of a) at least one embedded peripheral and b) at least one memory, and a bus monitor for allowing access to the at least one of a) the at least one embedded peripheral and b) the at least one memory, if the access is allowed, wherein the bus monitor comprises a mapping of access rights to the at least one of a) the at least one embedded peripheral and b) the at least one memory for the first processor and the second processor is disclosed.
摘要翻译：一种单芯片集成电路，包括用于执行多个应用的第一处理器，用于执行多个应用的第二处理器，至少一个嵌入式外围设备和b）至少一个存储器，以及总线监视器用于允许访问所述至少一个嵌入式外围设备中的至少一个;以及b）所述至少一个存储器，如果所述访问被允许，则所述总线监视器包括访问权限映射到以下至少一个：a）所述至少一个嵌入式外围设备和b）所述至少一个用于所述第一处理器和所述第二处理器的存储器。

6. 发明授权

US5414354A Apparatus and method for generating a substantially rectangular output signal 失效
标题翻译：用于产生大致矩形输出信号的装置和方法
公开(公告)号：US5414354A
公开(公告)日：1995-05-09
申请号：US103843
申请日：1993-08-09
申请人： Michael L. Bushman , Kenneth C. Fuchs
发明人： Michael L. Bushman , Kenneth C. Fuchs
IPC分类号： H03K5/003 , H03K5/12 , H03K5/156 , H03K12/00
CPC分类号： H03K5/003 , H03K5/12 , H03K5/1565
摘要： A squaring amplifier circuit (300) generates a substantially rectangular output signal from an a.c. input signal. An amplifier stage (303) is biased at a low quiescent current by a current source network (305) and a coupling network (306). Since the amplifier stage (303) current is a non-linear function of its input voltage, application of a low-level a.c. input signal (313), through an input signal coupling network (302), results in a substantially rectangular output signal having frequency and duty cycle that are substantially identical to the frequency and duty cycle of the input signal.
摘要翻译：平方放大器电路（300）从交流电源（300）产生基本矩形的输出信号。输入信号。放大器级（303）由电流源网络（305）和耦合网络（306）偏置在低静态电流。由于放大器级（303）的电流是其输入电压的非线性函数，因此应用低电平电流。输入信号（313）通过输入信号耦合网络（302）产生具有基本上与输入信号的频率和占空比相同的频率和占空比的基本上矩形的输出信号。

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