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    • 4. 发明授权
    • Semiconductor device including a TFT having large-grain polycrystalline active layer, LCD employing the same and method of fabricating them
    • 包括具有大晶粒多晶有源层的TFT的半导体器件,以及使用其的制造方法的半导体器件
    • US06274888B1
    • 2001-08-14
    • US09479919
    • 2000-01-10
    • Kenkichi SuzukiTetsuya NagataMichiko TakahashiMasakazu SaitoToshio OginoMasanobu Miyano
    • Kenkichi SuzukiTetsuya NagataMichiko TakahashiMasakazu SaitoToshio OginoMasanobu Miyano
    • H01L2904
    • H01L21/02672G02F1/13454H01L21/02675H01L21/02691H01L21/2022H01L21/2026H01L27/1277H01L27/1285H01L27/1296H01L29/04H01L29/66757H01L29/78675
    • A semiconductor device has a thin film transistor including an insulating substrate, an island made of a polycrystalline semiconductor material and disposed on the insulating substrate, a conductive layer made of the polycrystalline semiconductor material and at least one of metals and metallic silicides and surrounding the island, a source region and a drain region spaced from the source region, the source region and the drain region being formed in said island, a gate electrode disposed on the island with an insulating film interposed between the island and the gate electrode, the gate facing a spacing between the source region and the drain region. The polycrystalline semiconductor material forming the island and the conductive layer are fabricated by initially annealing a first amorphous semiconductor material deposited on the insulating substrate with a crystallization-inducing layer made of the at least one of metals and metallic silicides and having a hole corresponding to the island, the crystallization-inducing layer being disposed on a surface of the amorphous semiconductor material on at least one of a substrate side thereof and a side thereof opposite from the substrate side, and then by depositing a second amorphous semiconductor material on the first amorphous semiconductor and annealing the second amorphous semiconductor material.
    • 半导体器件具有薄膜晶体管,其包括绝缘基板,由多晶半导体材料制成并设置在绝缘基板上的岛,由多晶半导体材料制成的导电层和金属和金属硅化物中的至少一个并且围绕该岛 源极区域和漏极区域与源极区域间隔开,源极区域和漏极区域形成在所述岛状中,栅极电极设置在岛上,绝缘膜插入在岛状物和栅极电极之间,栅极面对 源极区域和漏极区域之间的间隔。 形成岛和导电层的多晶半导体材料通过用沉积在绝缘基板上的第一非晶半导体材料用由金属和金属硅化物中的至少一种制成的结晶诱导层进行初始退火而制造,并具有对应于 岛,所述结晶诱导层设置在所述非晶半导体材料的表面上的与所述基板侧相对的基板侧和侧面中的至少一个上,然后通过在所述第一非晶半导体上沉积第二非晶半导体材料 以及退火所述第二非晶半导体材料。
    • 8. 发明授权
    • Method and apparatus for adjusting the sampling phase of a digitally
encoded signal in a wireless communication system
    • 一种用于在无线通信系统中调整数字编码信号的采样相位的方法和装置
    • US5400368A
    • 1995-03-21
    • US107451
    • 1993-08-17
    • Jong-Keung ChengNan-Sheng LinMihran TouriguianKenkichi Suzuki
    • Jong-Keung ChengNan-Sheng LinMihran TouriguianKenkichi Suzuki
    • G01S11/10H04L7/033H04L7/04H04L7/00
    • G01S11/10H04L7/0334H04L7/042
    • In a digital wireless communication system, a first unit transmits a digitally encoded signal to a second unit in a plurality of non-contiguous time slots. Within each time slot, the digitally encoded signal has a synchronization signal portion followed by a data signal portion. The second unit has an antenna to receive the synchronization signal portion of the digitally encoded signal. The second unit also has a clock to generate a clock signal at a first rate having a sampling phase. An analog to digital converter receives the clock signal and the synchronization signal and samples the synchronization signal at the first rate to generate a first plurality of symbols. An interpolator receives the first plurality of symbols and interpolates the first plurality of symbols to generate a second plurality of symbols at a second rate. The second rate is a multiple of the first rate. A match filter receives the second plurality of symbols and compares the second plurality symbol of symbols to a stored plurality of symbols to generate an error signal. The sampling phase of the clock signal is altered in response to the error signal, after to the receipt of the synchronization signal.
    • 在数字无线通信系统中,第一单元将数字编码信号发送到多个非连续时隙中的第二单元。 在每个时隙内,数字编码的信号具有跟随数据信号部分的同步信号部分。 第二单元具有用于接收数字编码信号的同步信号部分的天线。 第二单元还具有用于以具有采样相位的第一速率产生时钟信号的时钟。 模数转换器接收时钟信号和同步信号,并以第一速率采样同步信号,以产生第一多个符号。 内插器接收第一多个符号并内插第一多个符号以产生第二个速率的第二个多个符号。 第二个利率是第一个利率的倍数。 匹配滤波器接收第二多个符号,并将第二多个符号符号与存储的多个符号进行比较,以产生误差信号。 在接收到同步信号之后,响应于误差信号改变时钟信号的采样相位。