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    • 2. 发明授权
    • Cylinder apparatus
    • 气缸装置
    • US08157276B2
    • 2012-04-17
    • US12785671
    • 2010-05-24
    • Kenji NodaYoshiaki Totani
    • Kenji NodaYoshiaki Totani
    • B60G21/05
    • F16F9/3257B60G21/0558F16F9/3242F16F9/325
    • A piston coupled to a piston rod is inserted in a cylinder, and an outer cylinder is disposed around the cylinder so as to define a reservoir therebetween. A separator tube is disposed around the cylinder so as to define an annular passage therebetween. The piston rod can be locked and unlocked by closing and opening an electromagnetic open/close valve so as to block and allow a flow of hydraulic fluid through a flow passage between the annular passage and the reservoir. The separator tube has a greater thickness. O-rings are disposed so as to provide seals between the separator tube and the cylinder. The separator tube extends to positions such that the ends of the separator tube overlap a base valve and a rod guide, thereby holding the respective ends of the cylinder. Due to this configuration, it is possible to prevent deformation of the cylinder and the separator tube due to an increase in the hydraulic pressure.
    • 联接到活塞杆的活塞插入到气缸中,并且外筒围绕气缸设置以在其间限定一个容器。 分隔管设置在圆筒周围,以便在它们之间限定环形通道。 活塞杆可以通过关闭和打开电磁开关阀而被锁定和解锁,以阻止和允许液压流体流过环形通道和储存器之间的流动通道。 分离管具有更大的厚度。 O形环被设置成在分离器管和气缸之间提供密封。 分离管延伸到使得分离管的端部与基座阀和杆引导件重叠的位置,从而保持气缸的相应端部。 由于这种构造,可以防止由于液压的增加而引起的气缸和分离管的变形。
    • 5. 发明授权
    • MIS-transistor-based nonvolatile memory for multilevel data storage
    • 用于多级数据存储的基于MIS晶体管的非易失性存储器
    • US07733714B2
    • 2010-06-08
    • US12139550
    • 2008-06-16
    • Tadahiko HoriuchiKenji Noda
    • Tadahiko HoriuchiKenji Noda
    • G11C7/00
    • G11C11/5671G11C2211/5642G11C2211/5647
    • A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.
    • 存储器电路包括具有第一节点和第二节点的锁存器,用于存储数据,使得第一节点的逻辑电平为第二节点的逻辑电平的倒数,具有门节点的MIS晶体管,第一源/ 漏极节点和第二源极/漏极节点,耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路,被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据,在第一操作中MIS晶体管的阈值电压的持续变化,并且响应于存储在锁存器中的数据,在第二操作中使阈值电压下降。
    • 6. 发明申请
    • Polybutylene terephthalate and process for producing thereof
    • 聚对苯二甲酸丁二醇酯及其制造方法
    • US20090054618A1
    • 2009-02-26
    • US11990916
    • 2006-08-28
    • Kenji NodaMasanori YamamotoShinichiro MatsuzonoToshiyuki HamanoYoshio AkahaneHidekazu Shouji
    • Kenji NodaMasanori YamamotoShinichiro MatsuzonoToshiyuki HamanoYoshio AkahaneHidekazu Shouji
    • C08G63/183C08G63/85
    • C08G63/85C08G63/80
    • An object of the present invention is to provide polybutylene terephthalate which has excellent color tone, hydrolysis resistance, heat stability, transparency and moldability as well as a less content of impurities, can be produced with maintaining its productivity while preventing from generation of tetrahydrofuran as a by-product, and can be suitably applied to films, monofilaments, fibers, electric and electronic parts, automobile parts, etc.In an aspect of the present invention, there is provided a process for continuously producing polybutylene terephthalate from terephthalic acid and 1,4-butanediol in a presence of a catalyst comprising a titanium compound and a compound of at least one metal selected from Group 1 and Group 2 of the Periodic Table, which process satisfies such the following requirements (a) to (c) that: (a) an oligomer is obtained by conducting a continuously esterification reaction of terephthalic acid and 1,4-butanediol in the presence of titanium catalyst in an amount of not more than 460 μmol as a titanium atom based on 1 mol of terephthalic acid unit; (b) polycondensation reaction of the said oligomer is continuously conducted in the presence of compound of at least one metal selected from Group 1 and Group 2 of the Periodic Table as the catalyst in an amount of not more than 450 μmol as the metal atom based on 1 mol of terephthalic acid unit; and (c) the said compound of at least one metal may be added to a stage before obtaining an oligomer having esterification conversion of not less than 90% in an amount of not more than 300 μmol as the metal atom based on 1 mol of terephthalic acid unit, and the said compound of at least one metal may be added to a stage on or after obtaining an oligomer having esterification conversion of not less than 90% in an amount of not less than 10 μmol as the metal atom based on 1 mol of terephthalic acid unit.
    • 本发明的目的是提供具有优异色调,耐水解性,热稳定性,透明性和成型性以及较少杂质含量的聚对苯二甲酸丁二醇酯,同时保持其生产率,同时防止产生四氢呋喃作为 副产物,可适用于薄膜,单丝,纤维,电气电子部件,汽车部件等。在本发明的一个方面,提供了一种从对苯二甲酸和1, 在包含钛化合物和选自元素周期表第1族和第2族中的至少一种金属的化合物的催化剂存在下,该方法满足以下要求(a)至(c):( a)通过在钛催化剂的存在下进行对苯二甲酸和1,4-丁二醇的连续酯化反应获得低聚物 相对于1摩尔对苯二甲酸单元,钛原子为460摩尔以下的量; (b)所述低聚物的缩聚反应在作为催化剂的至少一种选自元素周期表第1族和第2族的金属的化合物存在下连续进行,其金属原子数不超过450μmol 在1mol对苯二甲酸单元上; 和(c)所述至少一种金属的化合物可以在获得具有不低于90%的酯化转化率的低聚物之后的阶段中加入到作为金属原子的不超过300μmol的量,基于1mol对苯二甲酸 酸单元,并且所述至少一种金属的化合物可以在获得基于1摩尔的金属原子的不少于10摩尔的酯化转化率为90%以上的低聚物或其后添加 的对苯二甲酸单元。
    • 7. 发明授权
    • Nonvolatile memory device with test mechanism
    • 具有测试机制的非易失性存储器件
    • US07414903B2
    • 2008-08-19
    • US11413987
    • 2006-04-28
    • Kenji Noda
    • Kenji Noda
    • G11C29/00
    • G11C29/50G11C16/04G11C29/50016
    • A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.
    • 非易失性半导体存储器件包括具有MIS晶体管的存储单元,其被配置为经历其晶体管特性的不可逆变化以将数据存储为不可逆变化,所述MIS晶体管具有耦合到字选择线和源极/漏极节点 耦合到位线,并且所述MIS晶体管响应于所述字选择线的第一状态变为导通,并且响应于所述字选择线的第二状态变为不导通,以及耦合到所述位线以感测 电流流过MIS晶体管,测试电路被配置为响应于当字选择线处于第二状态时检测到电流的存在或者当字选择线处于第二状态时检测到电流的错误 第一个状态。
    • 8. 发明授权
    • Grinding process and apparatus with arrangement for grinding with constant grinding load
    • 磨削工艺和设备,具有磨削负载平稳的磨削
    • US07413499B2
    • 2008-08-19
    • US11236825
    • 2005-09-28
    • Kenji Noda
    • Kenji Noda
    • B24B1/00B24B49/00B24B51/00
    • B24B47/20B24B7/00B24B49/16
    • A process of grinding a surface of a workpiece, by a grinding tool rotated about its axis. The process includes a grinding step of grinding the workpiece surface, by pressing at least one of the grinding tool and the workpiece against the other of the grinding tool and the workpiece, such that a constant force is exerted on the other of the grinding tool and the workpiece by the at least one of the grinding tool and the workpiece. Also disclosed is a grinding apparatus including: a moving device operable to move at least one of the grinding tool and the workpiece relative to the other of the grinding tool and the workpiece, at least in an infeed direction that increases a depth of cut of the grinding tool into the workpiece; and a controller which controls the moving device, such that the at least one of the grinding tool and the workpiece is pressed against the other of the grinding tool and the workpiece, with a constant force.
    • 通过围绕其轴线旋转的研磨工具研磨工件的表面的工艺。 该方法包括:通过将磨削工具和工件中的至少一个压靠在研磨工具和工件中的另一个上来研磨工件表面的磨削步骤,使得恒定的力施加在研磨工具的另一个上,并且 所述工件由所述研磨工具中的至少一个和所述工件组成。 还公开了一种磨削装置,其包括:移动装置,其可操作以相对于研磨工具和工件中的另一个移动至少一个研磨工具和工件,至少在进给方向上,该进给方向增加了切削深度 研磨工具进入工件; 以及控制器,其控制所述移动装置,使得所述研磨工具和所述工件中的所述至少一个以恒定的力压在所述研磨工具和所述工件中的另一个上。
    • 9. 发明申请
    • Exposure apparatus and exposure method
    • 曝光装置和曝光方法
    • US20080129978A1
    • 2008-06-05
    • US11984351
    • 2007-11-16
    • Noritoshi TakadaSeiji TanakaKenji NodaHidekazu Kitahara
    • Noritoshi TakadaSeiji TanakaKenji NodaHidekazu Kitahara
    • G03B27/32
    • G03B27/32G03F9/7026G03F9/7034
    • According to an exposure apparatus and an exposure method in the present invention, based on a focus value and a leveling value in each exposure shot calculated based on measurements by a focus sensor, differential absolute values for respective values are calculated. The differential absolute values for the focus value and leveling value are compared with predetermined threshold value for the respective differential absolute values. When the differential absolute values exceed the threshold value, it is determined that an exposure abnormality exists. In such case, based on at least the number of exposure area where the exposure abnormality is occurred and distribution of the exposure area where the exposure abnormality is occurred on the object to be exposed, a kind of the exposure abnormality is identified. The detection of the exposure abnormality is assured, and a cause of the abnormality is determined without lowering manufacturing capabilities and increasing in costs.
    • 根据本发明的曝光装置和曝光方法,基于基于由聚焦传感器的测量计算的每个曝光拍摄中的对焦值和调平值,计算各个值的差分绝对值。 将对焦值和调平值的差分绝对值与各个差分绝对值的预定阈值进行比较。 当差分绝对值超过阈值时,确定存在曝光异常。 在这种情况下,基于至少暴露异常的曝光区域的数量和曝光对象物上的曝光​​异常的曝光区域的分布,识别曝光异常的种类。 确保曝光异常的检测,并且在不降低制造能力和成本增加的情况下确定异常的原因。
    • 10. 发明授权
    • Nonvolatile memory utilizing asymmetric characteristics of hot-carrier effect
    • 非易失性存储器利用热载体效应的不对称特性
    • US07321505B2
    • 2008-01-22
    • US11367952
    • 2006-03-03
    • Kenji Noda
    • Kenji Noda
    • G11C11/00
    • G11C8/08G11C7/1045G11C14/00G11C14/0063
    • A memory circuit includes a latch having a first node and a second node, a first MIS transistor having source/drain nodes thereof coupled to the first node and to a plate line, respectively, and a gate node thereof coupled to a word selecting line, a second MIS transistor having source/drain nodes thereof coupled to the second node and to the plate line, respectively, and a gate node thereof coupled to the word selecting line, and a driver circuit configured to set the plate line to a first potential causing the first node to serve as a source node of the first MIS transistor in a first operation mode and to a second potential causing the first node to serve as a drain node of the first MIS transistor in a second operation mode, the first operation mode causing a lingering change in characteristics of the first MIS transistor.
    • 存储电路包括具有第一节点和第二节点的锁存器,第一MIS晶体管分别具有耦合到第一节点和板线的源极/漏极节点,以及耦合到字选择线的栅极节点, 第二MIS晶体管,其源极/漏极节点分别耦合到第二节点和板极线,并且其栅极节点分别耦合到字选择线,以及驱动器电路,其被配置为将板线设置为第一电位, 所述第一节点在第一操作模式中用作所述第一MIS晶体管的源节点,以及在第二操作模式中使所述第一节点用作所述第一MIS晶体管的漏极节点的第二电位,所述第一操作模式导致 第一MIS晶体管的特性的持续变化。