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    • 9. 发明授权
    • Output buffer circuit having low breakdown voltage
    • 输出缓冲电路具有低击穿电压
    • US6064227A
    • 2000-05-16
    • US059248
    • 1998-04-14
    • Toshiaki Saito
    • Toshiaki Saito
    • H03K19/0185H03K19/003H03K19/0175H03K19/094H03K19/00H03K19/20G05K3/02
    • H03K19/00315
    • In an output buffer circuit, a logic circuit generates first and second data signals each having a voltage level between a low voltage and a first high voltage. A level shift circuit receives the first data signal and generates a third data signal having a voltage between a first intermediate voltage and a second high voltage higher than the first high voltage. An output circuit includes first and second P-channel MOS transistors and first and second N-channel MOS transistors powered by the low voltage and the second high voltage, a gate of the first P-channel MOS transistor receives the third data signal, a gate of the second P-channel MOS transistor receives a second intermediate voltage between the low voltage and the second high voltage, a gate of the first N-channel MOS transistor receives the data signal, and a gate of the second N-channel MOS transistor receives a third intermediate voltage.
    • 在输出缓冲器电路中,逻辑电路产生每个具有低电压和第一高电压之间的电压电平的第一和第二数据信号。 电平移位电路接收第一数据信号并产生具有高于第一高电压的第一中间电压和第二高电压之间的电压的第三数据信号。 输出电路包括第一和第二P沟道MOS晶体管以及由低电压和第二高电压供电的第一和第二N沟道MOS晶体管,第一P沟道MOS晶体管的栅极接收第三数据信号,栅极 所述第二P沟道MOS晶体管接收所述低电压和所述第二高电压之间的第二中间电压,所述第一N沟道MOS晶体管的栅极接收所述数据信号,并且所述第二N沟道MOS晶体管的栅极接收 第三中间电压。