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1. 发明申请

US20080265278A1 Semiconductor Device and Semiconductor Integrated Circuit Device for Driving Plasma Display Using the Semiconductor Device 失效
标题翻译：用于使用半导体器件驱动等离子体显示器的半导体器件和半导体集成电路器件
公开(公告)号：US20080265278A1
公开(公告)日：2008-10-30
申请号：US12103911
申请日：2008-04-16
申请人： Kenji Hara , Junichi Sakano , Shinji Shirakawa
发明人： Kenji Hara , Junichi Sakano , Shinji Shirakawa
IPC分类号： H01L29/739 , G09G5/00
CPC分类号： H01L29/7394 , G09G3/293 , G09G3/296 , G09G2330/04
摘要： A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.
摘要翻译：一种横向IGBT结构，其具有包括两个或更多个用于一个集电极端子的第二导电类型的基底层的发射极端子，其中发射极区域中的第二导电类型的基极层被第一导电类型层覆盖，所述第一导电类型层具有浓度高于漂移层的浓度，使得覆盖发射极区域的第一导电类型层和掩埋氧化物膜之间的硅层具有降低的电阻，从而增加流向离集电极更远的发射极的电流，从而提高电流密度。

2. 发明授权

US08487343B2 Semiconductor device, semiconductor integrated circuit device for use of driving plasma display with using same, and plasma display apparatus 失效
标题翻译：半导体装置，使用该驱动等离子体显示器的半导体集成电路装置以及等离子体显示装置
公开(公告)号：US08487343B2
公开(公告)日：2013-07-16
申请号：US12825839
申请日：2010-06-29
申请人： Shinji Shirakawa , Junichi Sakano , Kenji Hara
发明人： Shinji Shirakawa , Junichi Sakano , Kenji Hara
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , H01L29/0696
摘要： A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.
摘要翻译：形成在SOI衬底上的具有大电流密度的水平型IGBT具有发射极区域，其在氧化物膜沟槽上由二（2）个或更多个第二导电类型的基底层构成其特征在于，所述发射极区域中的所述第二导电型的基极层被覆盖有比漂移层高的导电性的第一导电型层，所述氧化物膜沟槽上的栅电极的长度为比集电体上的栅电极的长度小，并且在集电体上形成第二导电类型的基底层下方的第一导电型高密度层，从而实现层间的高密度化第一导电型，同时保持耐久电压，并增加电流密度。

3. 发明申请

US20100327315A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR USE OF DRIVING PLASMA DISPLAY WITH USING SAME, AND PLASMA DISPLAY APPARATUS 失效
标题翻译：半导体器件，用于驱动等离子体显示器的半导体集成电路装置以及等离子体显示装置
公开(公告)号：US20100327315A1
公开(公告)日：2010-12-30
申请号：US12825839
申请日：2010-06-29
申请人： Shinji SHIRAKAWA , Junichi Sakano , Kenji Hara
发明人： Shinji SHIRAKAWA , Junichi Sakano , Kenji Hara
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , H01L29/0696
摘要： A horizontal-type IGBT having a large current density, which is formed on a SOI substrate, has an emitter region, which is made up with two (2) or more of base-layers of a second conductivity-type on an oxide film groove, wherein the base-layers of the second conductivity-type in the emitter region are covered with a layer of a first conductivity-type, being high in the conductivity than a drift layer, and length of a gate electrode on the oxide film groove is reduced than the length of the gate electrode on the collector, and further the high-density layer of the first conductivity-type is formed below the base layer of the second conductivity-type on the collector, thereby achieving the high density of the layer of the first conductivity-type while maintaining an endurable voltage, and an increase of the current density.
摘要翻译：形成在SOI衬底上的具有大电流密度的水平型IGBT具有发射极区域，其在氧化物膜沟槽上由二（2）个或更多个第二导电类型的基底层构成其特征在于，所述发射极区域中的所述第二导电型的基极层被覆盖有比漂移层高的导电性的第一导电型层，所述氧化物膜沟槽上的栅电极的长度为比集电体上的栅电极的长度小，并且在集电体上形成第二导电类型的基底层下方的第一导电型高密度层，从而实现层间的高密度化第一导电型，同时保持耐久电压，并增加电流密度。

4. 发明申请

US20100219448A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR DRIVING PLASMA DISPLAY USING THE SEMICONDUCTOR DEVICE 失效
标题翻译：用半导体器件驱动等离子体显示的半导体器件和半导体集成电路器件
公开(公告)号：US20100219448A1
公开(公告)日：2010-09-02
申请号：US12707884
申请日：2010-02-18
申请人： Kenji HARA , Junichi Sakano , Shinji Shirakawa
发明人： Kenji HARA , Junichi Sakano , Shinji Shirakawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7394 , G09G3/296 , G09G2330/04 , H01L27/0248
摘要： The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.
摘要翻译：输出电路使用包含正常闩锁操作措施的IGBT，并且ESD钳位电路使用可以比具有防止闩锁的层的输出电路器件更容易闩锁的IGBT，该输出电路器件的杂质密度降低或去除。

5. 发明授权

US07586467B2 Load drive circuit, integrated circuit, and plasma display 有权
标题翻译：负载驱动电路，集成电路和等离子显示
公开(公告)号：US07586467B2
公开(公告)日：2009-09-08
申请号：US11434913
申请日：2006-05-17
申请人： Junichi Sakano , Kenji Hara , Mutsuhiro Mori
发明人： Junichi Sakano , Kenji Hara , Mutsuhiro Mori
IPC分类号： G09G3/28
CPC分类号： G09G3/296 , G09G2330/028 , Y10T307/461
摘要： A small-sized, low-loss load drive circuit, an integrated circuit for that drive circuit, and an inexpensive plasma display using that integrated circuit. In the load drive circuit that responds to switching commands to supply a high or low voltage to a load by switching, the source-drain voltage of an output-stage n-type MOS transistor of a flip-flop is supplied between the gate and cathode of a main IGBT. In order to hold this voltage, the power source to the flip-flop is supplied from a main power source or a charge pump power circuit connected at the fixed potential point of the main power source. In addition, a discharge prevention circuit and discharge prevention elements and are provided in order that the potential of the power source can be maintained higher than the positive potential of main power source.
摘要翻译：小型，低损耗负载驱动电路，用于该驱动电路的集成电路，以及使用该集成电路的便宜的等离子体显示器。在响应切换命令的负载驱动电路中，通过切换向负载提供高电压或低电压，触发器的输出级n型MOS晶体管的源极 - 漏极电压被提供在栅极和阴极之间的主要IGBT。为了保持该电压，触发器的电源从连接在主电源的固定电位点的主电源或电荷泵电源电路提供。此外，设置放电防止电路和放电防止元件，以使得电源的电位可以保持高于主电源的正电位。

6. 发明授权

US09190992B2 Semiconductor device and ultrasonic diagnostic apparatus using the same 有权
标题翻译：半导体装置及其使用的超声波诊断装置
公开(公告)号：US09190992B2
公开(公告)日：2015-11-17
申请号：US13282882
申请日：2011-10-27
申请人： Kenji Hara , Junichi Sakano
发明人： Kenji Hara , Junichi Sakano
IPC分类号： H03K17/687 , H03K17/06 , H03K17/081 , H03K17/10
CPC分类号： H03K17/063 , A61B8/4483 , H03K17/08104 , H03K17/102 , H03K17/6874
摘要： The present invention provides a semiconductor device of a bi-directional analog switch having a high linearity and a low electric power loss. An ultrasonic diagnostic apparatus having a high degree of detection accuracy, comprising the semiconductor device, is also provided. A semiconductor device of a bi-directional analog switch, comprising a switch circuit capable of switching ON or OFF bi-directionally, and built-in driving circuits for the switch circuit, wherein the driving circuit is connected to first and second power supplies, and a first power supply voltage is higher than a maximum voltage of a signal applied to an input/output terminal of the switch circuit, a second power supply voltage is lower than a minimum voltage of a signal applied to an input/output terminal of the switch circuit, and the driving circuit comprises a Zener diode and a p-type MOSFET connected in series between the first power supply and the switch circuit.
摘要翻译：本发明提供具有高线性度和低功率损耗的双向模拟开关的半导体器件。还提供了包括半导体器件的具有高检测精度的超声波诊断装置。一种双向模拟开关的半导体器件，包括能够双向接通或断开的开关电路和用于开关电路的内置驱动电路，其中驱动电路连接到第一和第二电源，以及第一电源电压高于施加到开关电路的输入/输出端子的信号的最大电压，第二电源电压低于施加到开关的输入/输出端子的信号的最小电压电路，并且驱动电路包括串联连接在第一电源和开关电路之间的齐纳二极管和p型MOSFET。

7. 发明授权

US07948058B2 Semiconductor device and semiconductor integrated circuit device for driving plasma display using the semiconductor device 失效
标题翻译：半导体装置及使用该半导体装置驱动等离子体显示的半导体集成电路装置
公开(公告)号：US07948058B2
公开(公告)日：2011-05-24
申请号：US12103911
申请日：2008-04-16
申请人： Kenji Hara , Junichi Sakano , Shinji Shirakawa
发明人： Kenji Hara , Junichi Sakano , Shinji Shirakawa
IPC分类号： H01L29/00
CPC分类号： H01L29/7394 , G09G3/293 , G09G3/296 , G09G2330/04
摘要： A lateral IGBT structure having an emitter terminal including two or more base layers of a second conductivity-type for one collector terminal, in which the base layers of a second conductivity-type in emitter regions are covered with a first conductivity-type layer having a concentration higher than that of a drift layer so that a silicon layer between the first conductivity-type layer covering the emitter regions and a buried oxide film has a reduced resistance to increase current flowing to an emitter farther from the collector to thereby enhance the current density.
摘要翻译：一种横向IGBT结构，其具有包括两个或更多个用于一个集电极端子的第二导电类型的基底层的发射极端子，其中发射极区域中的第二导电类型的基极层被第一导电类型层覆盖，所述第一导电类型层具有浓度高于漂移层的浓度，使得覆盖发射极区域的第一导电类型层和掩埋氧化物膜之间的硅层具有降低的电阻，从而增加流向离集电极更远的发射极的电流，从而提高电流密度。

8. 发明申请

US20100165681A1 SEMICONDUCTOR DEVICE AND POWER CONVERTER USING THE SAME 审中-公开
标题翻译：半导体器件和功率转换器
公开(公告)号：US20100165681A1
公开(公告)日：2010-07-01
申请号：US12646990
申请日：2009-12-24
申请人： Junichi Sakano , Kenji Hara , Shinji Shirakawa
发明人： Junichi Sakano , Kenji Hara , Shinji Shirakawa
IPC分类号： H02M7/06 , H03K17/687
CPC分类号： H03K17/163 , H03K17/6877
摘要： In a driving circuit, for controlling the turning on and off of a main semiconductor switching device of an insulated gate type, in an insulated gate semiconductor switching device for electric power conversion, bipolar semiconductor devices of an insulated gate control type, particularly insulated gate bipolar transistors (IGBTs) are used at the output stage of a circuit that controls the gate voltage of the main semiconductor switching device.
摘要翻译：在用于控制绝缘栅型主半导体开关器件的导通和截止的驱动电路中，在用于电力转换的绝缘栅半导体开关器件中，绝缘栅极控制型双极半导体器件，特别是绝缘栅极双极型在控制主半导体开关器件的栅极电压的电路的输出级使用晶体管（IGBT）。

9. 发明申请

US20120108963A1 Semiconductor Device and Ultrasonic Diagnostic Apparatus Using the Same 有权
标题翻译：半导体装置及其使用的超声波诊断装置
公开(公告)号：US20120108963A1
公开(公告)日：2012-05-03
申请号：US13282882
申请日：2011-10-27
申请人： Kenji HARA , Junichi Sakano
发明人： Kenji HARA , Junichi Sakano
IPC分类号： A61B8/00 , H03L5/00 , H03K17/687
CPC分类号： H03K17/063 , A61B8/4483 , H03K17/08104 , H03K17/102 , H03K17/6874
摘要： The present invention provides a semiconductor device of a bi-directional analog switch having a high linearity and a low electric power loss. An ultrasonic diagnostic apparatus having a high degree of detection accuracy, comprising the semiconductor device, is also provided. A semiconductor device of a bi-directional analog switch, comprising a switch circuit capable of switching ON or OFF bi-directionally, and built-in driving circuits for the switch circuit, wherein the driving circuit is connected to first and second power supplies, and a first power supply voltage is higher than a maximum voltage of a signal applied to an input/output terminal of the switch circuit, a second power supply voltage is lower than a minimum voltage of a signal applied to an input/output terminal of the switch circuit, and the driving circuit comprises a Zener diode and a p-type MOSFET connected in series between the first power supply and the switch circuit.
摘要翻译：本发明提供具有高线性度和低功率损耗的双向模拟开关的半导体器件。还提供了包括半导体器件的具有高检测精度的超声波诊断装置。一种双向模拟开关的半导体器件，包括能够双向接通或断开的开关电路和用于开关电路的内置驱动电路，其中驱动电路连接到第一和第二电源，以及第一电源电压高于施加到开关电路的输入/输出端子的信号的最大电压，第二电源电压低于施加到开关的输入/输出端子的信号的最小电压电路，并且驱动电路包括串联连接在第一电源和开关电路之间的齐纳二极管和p型MOSFET。

10. 发明申请

US20080265331A1 Manufacturing method of semiconductor apparatus and semiconductor apparatus, power converter using the same 有权
标题翻译：半导体装置和半导体装置的制造方法，使用其的功率转换器
公开(公告)号：US20080265331A1
公开(公告)日：2008-10-30
申请号：US12103921
申请日：2008-04-16
申请人： Junichi Sakano , Kenji Hara , Shinji Shirakawa , Taiga Arai , Mutsuhiro Mori
发明人： Junichi Sakano , Kenji Hara , Shinji Shirakawa , Taiga Arai , Mutsuhiro Mori
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L29/7394 , H01L29/0878 , H01L29/66325 , H01L29/66681 , H01L29/7824
摘要： In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm−3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.
摘要翻译：在通过绝缘膜形成在支撑基板上的SOI型高耐受电压半导体器件的制造方法中，通过将杂质引入p型或者p型的整个表面来制造具有小耐受电压的小分散的小型半导体器件 n型SOI衬底，其杂质浓度为2E14cm -3或更小，并且用离子注入方法用作半导体器件的有源层，从而形成漂移层。

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