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1. 发明授权

US06949969B2 Semiconductor device having relief circuit for relieving defective portion 失效
标题翻译：具有用于消除缺陷部分的释放电路的半导体装置
公开(公告)号：US06949969B2
公开(公告)日：2005-09-27
申请号：US10414226
申请日：2003-04-16
申请人： Kenichiro Mimoto , Takehiko Hojo
发明人： Kenichiro Mimoto , Takehiko Hojo
IPC分类号： G01R31/28 , G11C29/00 , G11C29/04 , H01H85/00 , H01L21/00 , H01L21/82 , H01L21/822 , H01L23/525 , H01L27/00 , H01L27/04 , H02B1/26
CPC分类号： G11C29/787 , G11C29/72 , G11C29/808 , G11C29/838
摘要： A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.
摘要翻译：半导体器件包括解除对象电路，浮雕电路和多个熔丝元件。救济对象电路实现预定的功能。提供释放电路以便释放救济对象电路以实现预定功能。多个保险丝元件相应于释放电路设置，以便用释放电路代替救济对象电路，从而存储当释放电路被释放电路代替时指定救济对象电路的信息。

2. 发明授权

US5929469A Contact holes of a different pitch in an application specific integrated circuit 失效
标题翻译：在专用集成电路中具有不同音高的接触孔
公开(公告)号：US5929469A
公开(公告)日：1999-07-27
申请号：US992542
申请日：1997-12-17
申请人： Kenichiro Mimoto , Motohiro Enkaku , Takehiko Hojo
发明人： Kenichiro Mimoto , Motohiro Enkaku , Takehiko Hojo
IPC分类号： H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/8234 , H01L23/52 , H01L27/088 , H01L27/118
CPC分类号： H01L27/11807 , H01L2924/0002
摘要： In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.
摘要翻译：在构成门阵列的基本单元的源极/漏极区域上方的第一层间绝缘膜中，放置第一接触孔（接合触点），使得通过插头在源极/漏极区域中电连接的翼（接合板）接头接点局部放置在源极/漏极区域之上。翼上方形成有第二层间绝缘膜，其上形成有构成金属布线层之一的第一层互连。在第二层间绝缘体膜中形成第二接触孔，从而提供半定制ASIC，其中翼和第一级互连通过那些第二接触孔中的插塞电互连。通过使用基于基本单元格中的网格图案的计算机来自动设计第一和第二接触孔，第一层互连等。根据本发明，即使第一接触孔的图案的第一间距与第二接触孔的图案的第二间距不同，基本单元也不需要重新设计，因此容易实现自动定制。在不增加基本单元中的源极/漏极区域的面积的情况下，可以选择布线层的任何间距，从而在降低定制所需时间的同时增加集成密度，而不会降低MOS FET的性能。

3. 发明授权

US06326693B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06326693B1
公开(公告)日：2001-12-04
申请号：US09372992
申请日：1999-08-12
申请人： Kenichiro Mimoto , Takehiko Hojo
发明人： Kenichiro Mimoto , Takehiko Hojo
IPC分类号： H01L2348
CPC分类号： H01L23/5286 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H01L2924/00
摘要： A semiconductor integrated circuit device has core circuits having rectangular shapes in plan view and power lines surronding the core circuit to connect the cores with an external power supply. The power lines are constructed in a plurality of interconnection layers and include interlayer connections so that they have overlapping parts. Interconnections between core circuits are commonly used so as to decrease interconnection area.
摘要翻译：半导体集成电路器件具有在平面图中具有矩形形状的核心电路以及绕着该核心电路的电源线，以将该核与外部电源连接。电力线构造在多个互连层中，并且包括层间连接，使得它们具有重叠部分。通常使用核心电路之间的互连，以减少互连区域。

4. 发明申请

US20060002205A1 Semiconductor device having relief circuit for relieving defective portion 审中-公开
标题翻译：具有用于消除缺陷部分的释放电路的半导体装置
公开(公告)号：US20060002205A1
公开(公告)日：2006-01-05
申请号：US11178469
申请日：2005-07-12
申请人： Kenichiro Mimoto , Takehiko Hojo
发明人： Kenichiro Mimoto , Takehiko Hojo
IPC分类号： G11C29/00
CPC分类号： G11C29/787 , G11C29/72 , G11C29/808 , G11C29/838
摘要： A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.
摘要翻译：半导体器件包括解除对象电路，浮雕电路和多个熔丝元件。救济对象电路实现预定的功能。提供释放电路以便释放救济对象电路以实现预定功能。多个保险丝元件相应于释放电路设置，以便用释放电路代替救济对象电路，从而存储当释放电路被释放电路代替时指定救济对象电路的信息。

5. 发明申请

US20060077732A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20060077732A1
公开(公告)日：2006-04-13
申请号：US11076633
申请日：2005-03-09
申请人： Takehiko Hojo
发明人： Takehiko Hojo
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value of the normal data is changed or not, and a determination circuit which determines whether a value of the normal data is changed or not based on the determination information. The capacitance of a data storage node of the second memory circuit is larger than that of a data storage node of the first memory circuit.
摘要翻译：一种半导体集成电路器件，包括存储正常数据的第一存储器电路，存储用于确定正常数据的值是否改变的确定信息的第二存储器电路，以及确定正常值的值的确定电路基于确定信息改变或不改变数据。第二存储器电路的数据存储节点的电容大于第一存储器电路的数据存储节点的电容。

6. 发明授权

US06985395B2 Semiconductor memory device and method of testing the device 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US06985395B2
公开(公告)日：2006-01-10
申请号：US10884105
申请日：2004-07-01
申请人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
发明人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
IPC分类号： G11C7/00
CPC分类号： G11C29/44
摘要： A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译：公开了一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括以行和列排列的存储单元，字线，位线，行解码器和列解码器，为存储器的每列提供的读出放大器单元阵列，写锁存电路，被配置为存储外部输入数据，并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路，被配置为存储从存储器读取的一行数据单元阵列，并且在测试模式下设置在读出放大器中，第一比较电路，被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器，被配置为存储比较结果第一个比较电路。

7. 发明申请

US20050068816A1 Semiconductor memory device and method of testing the device 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20050068816A1
公开(公告)日：2005-03-31
申请号：US10884105
申请日：2004-07-01
申请人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
发明人： Takanori Yoshimatsu , Takehiko Hojo , Kaoru Tokushige
IPC分类号： G11C29/12 , G11C11/401 , G11C29/04 , G11C29/44 , G11C7/00
CPC分类号： G11C29/44
摘要： A semiconductor memory device is disclosed, which comprises a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.
摘要翻译：公开了一种半导体存储器件，其包括存储单元阵列，该存储单元阵列包括以行和列排列的存储单元，字线，位线，行解码器和列解码器，为存储器的每列提供的读出放大器单元阵列，写锁存电路，被配置为存储外部输入数据，并以测试模式设置读出放大器中的一行存储单元阵列的数据;读锁存器电路，被配置为存储从存储器读取的一行数据单元阵列，并且在测试模式下设置在读出放大器中，第一比较电路，被配置为将存储在写入锁存电路中的数据与存储在读取锁存电路中的数据进行比较;第一比较结果寄存器，被配置为存储比较结果第一个比较电路。

8. 发明申请

US20120195092A1 ROM GENERATOR 审中-公开
标题翻译： ROM发电机
公开(公告)号：US20120195092A1
公开(公告)日：2012-08-02
申请号：US13444949
申请日：2012-04-12
申请人： Koji Kohara , Takehiko Hojo
发明人： Koji Kohara , Takehiko Hojo
IPC分类号： G11C17/08
CPC分类号： G11C17/14 , H01L27/0207 , H01L27/112 , H01L27/11226
摘要： According to one embodiment, a ROM generator includes a ROM-data acquiring unit that acquires ROM data; a cell-data storing unit that stores a plurality of cell data respectively having different connection places of a connection path with respect to same ROM data; a cell-data selecting unit that selects the cell data stored in the cell data storing unit with respect to the same ROM data acquired by the ROM-data acquiring unit; and a cell-data arranging unit that arranges the cell data selected by the cell-data selecting unit to correspond to cell regions.
摘要翻译：根据一个实施例，ROM生成器包括：ROM数据获取单元，其获取ROM数据; 单元数据存储单元，其相对于相同的ROM数据存储分别具有连接路径的不同连接位置的多个单元数据; 单元数据选择单元，根据由ROM数据获取单元获取的相同ROM数据，选择存储在单元数据存储单元中的单元数据; 以及单元数据排列单元，其将由所述单元数据选择单元选择的单元数据配置为对应于单元区域。

9. 发明授权

US07782662B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07782662B2
公开(公告)日：2010-08-24
申请号：US12181926
申请日：2008-07-29
申请人： Masaharu Wada , Takehiko Hojo
发明人： Masaharu Wada , Takehiko Hojo
IPC分类号： G11C11/50 , G11C5/06 , G11C11/00
CPC分类号： G11C17/16 , G11C13/00 , G11C13/004 , G11C13/0069
摘要： A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through the first contact, the wiring, and the second contact, and changing resistance values of the first contact to write information; and a read switching circuit controlling current for reading information that flows through the first contact, the wiring, and the third contact.
摘要翻译：存储装置包括：包括具有第一导电性的第一导体的布线; 以及第一，第二和第三触点，每个包括具有第二导电性的第二导体并接触布线。存储装置还包括：写入切换电路，控制用于写入流经第一触点，布线和第二触点的信息的电流，以及改变第一触点的电阻值以写入信息; 以及读取切换电路，控制用于读取流过第一触点，布线和第三触点的信息的电流。

10. 发明授权

US06928594B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06928594B2
公开(公告)日：2005-08-09
申请号：US09821163
申请日：2001-03-28
申请人： Toshiyuki Kouchi , Yoshinori Sugisawa , Takehiko Hojo
发明人： Toshiyuki Kouchi , Yoshinori Sugisawa , Takehiko Hojo
IPC分类号： G11C11/401 , G11C7/10 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/14 , G11C29/26 , G11C29/46 , H01L21/822 , H01L27/04 , G06F12/00 , G06F13/00
CPC分类号： G11C7/1057 , G11C7/1012 , G11C7/1051 , G11C29/10 , G11C29/14 , G11C29/26 , G11C29/46 , G11C2207/104
摘要： A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.
摘要翻译：公开了DRAM LSI中的逻辑，其包括多个DRAM电路，控制电路，其接收测试控制信号以执行其中多个RAM电路被测试的测试控制，同时对多个DRAM电路的访问随后对于每行而言，由控制电路控制的输入选择器，并且在测试时将DRAM宏信号输入到多个DRAM电路，以及由控制电路控制的输出选择器，并输出输出信号的多个DRAM电路在测试时顺序地送到宏输出端。根据DRAM集成LSI，集成在LSI中的多个DRAM电路的测试所需的测试时间缩短。此外，从多个DRAM电路读取的数据被高速传送。

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