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1. 发明授权

US07129565B2 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
公开(公告)号：US07129565B2
公开(公告)日：2006-10-31
申请号：US10349934
申请日：2003-01-24
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： H01L23/544
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

2. 发明申请

US20060194124A1 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
公开(公告)号：US20060194124A1
公开(公告)日：2006-08-31
申请号：US11352273
申请日：2006-02-13
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

3. 发明授权

US08507377B2 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
标题翻译：半导体装置及其制造方法以及相移掩模
公开(公告)号：US08507377B2
公开(公告)日：2013-08-13
申请号：US12764210
申请日：2010-04-21
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： H01L21/4763
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.
摘要翻译：一种制造半导体器件的方法，包括形成有集成电路的集成电路部分和包括围绕所述集成电路部分的金属膜的主壁部分的步骤包括以下步骤：在集成电路部分之间选择性地形成包括金属膜的副壁部分电路部分和主壁部分，并联形成集成电路部分和主壁部分。在主壁部的每个角部和所得到的半导体器件的集成电路部分之间设置有“L”形的副壁部。

4. 发明授权

US07755169B2 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
标题翻译：半导体装置及其制造方法以及相移掩模
公开(公告)号：US07755169B2
公开(公告)日：2010-07-13
申请号：US12357919
申请日：2009-01-22
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： H01L23/544
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
摘要翻译：主壁部设置为围绕集成电路部。在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生艺术。此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。因此，可以确保极高的耐湿性。

5. 发明授权

US07498659B2 Semiconductor device, method of manufacturing the same, and phase shift mask 有权
标题翻译：半导体装置及其制造方法以及相移掩模
公开(公告)号：US07498659B2
公开(公告)日：2009-03-03
申请号：US11352273
申请日：2006-02-13
申请人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
发明人： Kenichi Watanabe , Michiari Kawano , Hiroshi Namba , Kazuo Sukegawa , Takumi Hasegawa , Toyoji Sawada
IPC分类号： H01L23/544
CPC分类号： G03F1/26 , G03F1/32 , H01L21/76811 , H01L21/76813 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2221/1036 , H01L2924/0002 , H01L2924/01078 , H01L2924/3025 , H01L2924/00
摘要： A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.
摘要翻译：主壁部设置为围绕集成电路部。在主壁部的各个角部和集成电路部之间设置有“L”形的副壁部。因此，即使由于热处理等引起的应力集中，与常规的相比也不容易发生应力分散到主壁部和副壁部，因此层之间的剥离和裂纹不可能发生艺术。此外，即使在角部发生裂纹等，当主壁部和副壁部彼此结合时，来自外部的水分几乎不到达集成电路部。因此，可以确保极高的耐湿性。

6. 发明授权

US07119439B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US07119439B2
公开(公告)日：2006-10-10
申请号：US10454667
申请日：2003-06-05
申请人： Kenichi Watanabe , Michiari Kawano
发明人： Kenichi Watanabe , Michiari Kawano
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L21/76847 , H01L21/76852 , H01L23/53238 , H01L23/564 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.

7. 发明授权

US07241676B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07241676B2
公开(公告)日：2007-07-10
申请号：US10948569
申请日：2004-09-24
申请人： Kenichi Watanabe , Michiari Kawano
发明人： Kenichi Watanabe , Michiari Kawano
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L21/76847 , H01L21/76852 , H01L23/53238 , H01L23/564 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.
摘要翻译：在半导体衬底上形成接触图形之后，在接触图形上形成由第一阻挡金属膜和第一导体图案构成的第一布线图案。形成防潮环，其具有使第一阻挡金属膜的覆盖第一导体图案的外周侧的侧壁面的外周部与上端部接触的结构，阻挡金属底面部分，覆盖第二阻挡金属膜的通孔接触部分的底面。这导致在从半导体衬底到作为最上层的氧化硅膜的整个区域中形成诸如Ta，TiN等的阻挡金属膜，而不会中断，从而提高用于防止裂纹和入口的粘附性的水分。

8. 发明申请

US20050042816A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050042816A1
公开(公告)日：2005-02-24
申请号：US10948569
申请日：2004-09-24
申请人： Kenichi Watanabe , Michiari Kawano
发明人： Kenichi Watanabe , Michiari Kawano
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/00 , H01L23/522 , H01L23/532 , H01L21/8238
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76808 , H01L21/76813 , H01L21/76838 , H01L21/76847 , H01L21/76852 , H01L23/53238 , H01L23/564 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.
摘要翻译：在半导体衬底上形成接触图形之后，在接触图形上形成由第一阻挡金属膜和第一导体图案构成的第一布线图案。形成防潮环，其具有使第一阻挡金属膜的覆盖第一导体图案的外周侧的侧壁面的外周部与上端部接触的结构，阻挡金属底面部分，覆盖第二阻挡金属膜的通孔接触部分的底面。这导致在从半导体衬底到作为最上层的氧化硅膜的整个区域中形成诸如Ta，TiN等的阻挡金属膜，而不会中断，从而提高用于防止裂纹和入口的粘附性的水分。

9. 发明授权

US06433381B1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06433381B1
公开(公告)日：2002-08-13
申请号：US09756222
申请日：2001-01-09
申请人： Kazuhiro Mizutani , Michiari Kawano
发明人： Kazuhiro Mizutani , Michiari Kawano
IPC分类号： H01L27108
摘要： There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

10. 发明授权

US06794244B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06794244B2
公开(公告)日：2004-09-21
申请号：US10173595
申请日：2002-06-19
申请人： Kazuhiro Mizutani , Michiari Kawano
发明人： Kazuhiro Mizutani , Michiari Kawano
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76834 , H01L21/76838 , H01L21/76883 , H01L21/76895 , H01L21/76897 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.
摘要翻译：提供了具有COB型DRAM的半导体器件，其包括形成在半导体衬底上的第一绝缘膜，形成在第一区域中的第一绝缘膜中的第一布线沟槽，在第二绝缘膜中形成的第二布线沟槽区域具有与第一布线沟槽基本相同的深度，埋在第一布线沟槽的下部的第一布线，埋在第一布线沟槽的上部并由不同于第一绝缘膜的材料形成的第二绝缘膜，以及第二布线由与第二布线沟槽中的第一布线相同的导电材料形成并且形成为比第一布线更厚。因此，可以提高具有不同膜厚度的位线和布线的图案精度，并且以自对准方式形成在位线之间的通孔形成浅，并且还具有位线和布线减少。

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