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    • 4. 发明授权
    • Method of forming wirings for integrated circuits by electroplating
    • 通过电镀形成集成电路布线的方法
    • US5556814A
    • 1996-09-17
    • US410744
    • 1995-03-27
    • Tomotoshi InoueMisao Yoshimura
    • Tomotoshi InoueMisao Yoshimura
    • H01L23/52H01L21/3205H01L21/60H01L21/768H01L21/02
    • H01L21/76885H01L2924/0002
    • A method for forming wirings of an integrated circuit comprises a step of forming wirings on a substrate, a step of coating the wirings with a thin under metal layer, a step of coating the under metal layer with a mask except a part of the under metal layer, a first etching step of removing the under metal layer which is not coated by the mask to expose upper portions of at least ones of the wirings, an electroplating step of depositing a plating metal layer on the exposed upper portions, a step of removing the mask, and a second etching step of removing all of the remaining under metal layer, whereby said plating metal layer is formed by substantially same material as that of the exposed upper portions or by a material which can be closely contacted with the exposed upper portions and whereby said under metal layer is formed by a material which can be preferentially removed from the exposed upper portions.
    • 一种用于形成集成电路的配线的方法包括在基板上形成布线的步骤,用薄的金属下层涂覆布线的步骤,用除了金属以外的部分的掩模涂覆下金属层的步骤 层,第一蚀刻步骤,去除未被掩模涂覆的下金属层以暴露至少一个布线的上部;电镀步骤,在暴露的上部上沉积电镀金属层;除去 掩模和第二蚀刻步骤,去除所有剩余的下层金属层,由此所述电镀金属层由与暴露的上部的材料基本相同的材料形成,或通过与暴露的上部部分紧密接触的材料形成 并且由此所述下金属层由可以从暴露的上部优先除去的材料形成。