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1. 发明授权

US06114195A Manufacturing method of compound semiconductor field effect transistor 失效
标题翻译：化合物半导体场效应晶体管的制造方法
公开(公告)号：US06114195A
公开(公告)日：2000-09-05
申请号：US192575
申请日：1998-11-17
申请人： Kazuya Nishihori , Yoshiaki Kitaura , Naotaka Uchitomi
发明人： Kazuya Nishihori , Yoshiaki Kitaura , Naotaka Uchitomi
IPC分类号： H01L21/265 , H01L21/335 , H01L21/338 , H01L29/812
CPC分类号： H01L29/66462 , H01L29/66878
摘要： A manufacturing method of compound semiconductor field effect transistor capable of enhancing a gate/drain withstand voltage includes a step of forming a channel layer by implanting ions into the surface of a semi-insulating compound semiconductor substrate and a step of performing a first thermal treatment for removing crystalline defects on the surface of the channel layer. This method also includes a step of forming a compound semiconductor epitaxial layer by use of an epitaxial method on a region covering the channel layer, a step of forming a gate electrode within a region on the epitaxial layer just above the channel layer and a step of forming a source region and a drain region in the substrate. A concentration of the impurity for forming the channel layer at an interface between the channel layer and the epitaxial layer is 45% or under of the highest concentration when forming the channel layer. A good interface between the channel layer and the epitaxial layer can be thereby obtained, and a transistor having the high-quality epitaxial layer can be also acquired.
摘要翻译：能够提高栅极/漏极耐电压的化合物半导体场效应晶体管的制造方法包括通过将离子注入到半绝缘化合物半导体基板的表面中而形成沟道层的步骤，以及对半导体衬底的表面进行第一热处理的步骤去除沟道层表面的晶体缺陷。该方法还包括在覆盖沟道层的区域上利用外延法形成化合物半导体外延层的步骤，在沟道层正上方的外延层的区域内形成栅极电极的工序; 在衬底中形成源区和漏区。在形成沟道层时，在沟道层和外延层之间的界面处形成沟道层的杂质浓度为最高浓度的45％以下。由此可以获得沟道层和外延层之间的良好的界面，并且也可以获得具有高质量外延层的晶体管。

2. 发明授权

US5273937A Metal semiconductor device and method for producing the same 失效
标题翻译：金属半导体器件及其制造方法
公开(公告)号：US5273937A
公开(公告)日：1993-12-28
申请号：US774169
申请日：1991-10-15
申请人： Kazuya Nishihori , Tomotoshi Inoue , Kenichi Tomita , Hitoshi Mikami , Masami Nagaoka , Naotaka Uchitomi
发明人： Kazuya Nishihori , Tomotoshi Inoue , Kenichi Tomita , Hitoshi Mikami , Masami Nagaoka , Naotaka Uchitomi
IPC分类号： H01L29/47 , H01L21/283
CPC分类号： H01L29/475
摘要： A metal semiconductor device, in which an electrode is formed on a semiconductor substrate to form a Schottky junction therebetween, and the electrode has an oxide film having a first thickness on its upper surface and a non-oxidized portion having a second thickness from the Schottky junction. A method for producing the metal semiconductor device is also disclosed, in which a conductor layer formed on the semiconductor substrate is oxidized in a gas containing oxygen, and a capless annealing of the semiconductor substrate having the oxidized conductor layer thereon is conducted in an atmosphere containing arsenic.
摘要翻译：一种金属半导体器件，其中电极形成在半导体衬底上以在其间形成肖特基结，并且电极在其上表面具有第一厚度的氧化物膜和具有来自肖特基的第二厚度的非氧化部分交界处还公开了一种制造金属半导体器件的方法，其中形成在半导体衬底上的导体层在含氧气体中被氧化，并且在其上具有氧化的导体层的半导体衬底的无限退火在含有砷。

3. 发明授权

US5015596A Method of making a GaAs JFET with self-aligned p-type gate by outdiffusion of dopont from the metallic gate 失效
标题翻译：通过从金属栅极扩散dopont制造具有自对准p型栅极的GaAs JFET的方法
公开(公告)号：US5015596A
公开(公告)日：1991-05-14
申请号：US476140
申请日：1990-02-08
申请人： Nobuyuki Toyoda , Naotaka Uchitomi , Akimichi Hojo
发明人： Nobuyuki Toyoda , Naotaka Uchitomi , Akimichi Hojo
IPC分类号： H01L21/337 , H01L29/417 , H01L29/45 , H01L29/808
CPC分类号： H01L29/808 , H01L29/452 , Y10S148/082 , Y10S148/088
摘要： A GaAs JFET according to the present invention is formed as follows. First, an n type active layer is formed on a GaAs substrate. Then, a gate electrode containing a group II element is formed on the n type active layer. With the gate electrode being used as a mask, an n type impurity is ion-implanted in the GaAs substrate with a high concentration in a self-aligned fashion with respect to the gate electrode. Heat-treatment is then performed on the resultant structure to diffuse the group II element in the gate electrode into the n type active layer, forming a p type gate region. At the same time, the ion-implanted n type impurity is activated, forming source and drain regions.
摘要翻译：根据本发明的GaAs JFET如下形成。首先，在GaAs衬底上形成n型有源层。然后，在n型有源层上形成含有II族元素的栅电极。以栅电极作为掩模，n型杂质以相对于栅电极的自对准方式以高浓度离子注入到GaAs衬底中。然后在所得结构上进行热处理，将栅电极中的II族元素扩散到n型有源层中，形成p型栅区。同时，离子注入的n型杂质被激活，形成源区和漏区。

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